Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2703383

1

T2

72

T4

68

T5

117

full_word

1713634

1

T2

8

T4

5

T5

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4416667	1			T2	80		T4	73		T5	128
auto[TlIntgErrCmd]	110	1			T59	3		T60	7		T61	4
auto[TlIntgErrData]	115	1			T59	2		T60	5		T61	9
auto[TlIntgErrBoth]	125	1			T59	5		T60	8		T61	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703598

1

T2

80

T4

73

T5

128

auto[1]

3713419

1

T13

125163

T16

306566

T17

152686

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	297934	1			T2	72		T4	68		T5	117
auto[TlIntgErrNone]	partial	auto[1]	2405130	1			T13	81205		T16	199934		T17	97584
auto[TlIntgErrNone]	full_word	auto[0]	405520	1			T2	8		T4	5		T5	11
auto[TlIntgErrNone]	full_word	auto[1]	1308083	1			T13	43958		T16	106632		T17	55102
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T59	2		T60	5		T61	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T59	1		T60	2		T61	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T61	1		T102	1		T101	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T107	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T59	1		T60	2		T61	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T59	1		T60	2		T61	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T99	1		T102	1		T108	2
auto[TlIntgErrData]	full_word	auto[1]	9	1			T60	1		T99	1		T100	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T59	2		T60	2		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T59	3		T60	6		T61	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T101	2		T107	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T99	1		T102	1		T100	1