Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	97.10	83.74			89.66	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tl_adapter_rom	92.62	97.10	83.74			89.66	100.00

---

Module Instance : tb.dut.u_tl_adapter_rom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	97.10	83.74			89.66	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.23	91.60	85.20	99.07		95.29	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.98	100.00	98.28	97.33		100.00	79.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	100.00	100.00		100.00			100.00
u_err	100.00	100.00	100.00			100.00	100.00
u_reqfifo	96.53	100.00	86.11			100.00	100.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	95.02	100.00	85.11	90.00		100.00	100.00
u_sram_byte	100.00	100.00					100.00
u_sramreqfifo	92.36	100.00	75.00			94.44	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		69	67	97.10
CONT_ASSIGN	102	0	0
CONT_ASSIGN	109	0	0
ALWAYS	124	4	3	75.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
ALWAYS	266	8	7	87.50
ALWAYS	286	6	6	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
ALWAYS	349	3	3	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
ALWAYS	409	6	6	100.00
ALWAYS	421	5	5	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
ALWAYS	476	3	3	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	507	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
102		unreachable
109		unreachable
124	1	1
125	1	1
126	1	1
127	0	1
			MISSING_ELSE
133	1	1
138	1	1
145	1	1
150	1	1
170	1	1
182	1	1
259	1	1
260	1	1
261	1	1
266	1	1
268	1	1
269	1	1
271	1	1
272	1	1
273	1	1
276	0	1
279	1	1
286	1	1
288	1	1
289	1	1
290	1	1
292	1	1
295	1	1
300	1	1
304	1	1
323	1	1
328	1	1
334	1	1
346	1	1
349	1	1
350	1	1
352	1	1
356	1	1
376	1	1
377	1	1
378	1	1
379	1	1
409	1	1
410	1	1
412	1	1
413	1	1
414	1	1
415	1	1
			MISSING_ELSE
421	1	1
422	1	1
424	1	1
425	1	1
426	1	1
			MISSING_ELSE
432	1	1
433	1	1
442	1	1
443	1	1
445	1	1
446	1	1
453	1	1
456	1	1
460	1	1
461	1	1
463	1	1
470	1	1
476	1	1
480	1	1
482	1	1
			MISSING_ELSE
497	1	1
502	1	1
507		unreachable

---

Cond Coverage for Module : tlul_adapter_sram

	Total	Covered	Percent
Conditions	123	103	83.74
Logical	123	103	83.74
Non-Logical	0	0
Event	0	0

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T14,T15

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T15

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T15

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T13,T14,T15

 LINE       150
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T15

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T4,T5
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Covered	T13,T14,T15
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Covered	T13,T16,T17
1	0	0	0	0	0	Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T9
1	1	Covered	T2,T4,T5

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T4,T5

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T16,T17
1	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T13,T16,T17
1	0	Not Covered

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T13,T16,T17
1	1	1	0	Covered	T18
1	1	1	1	Covered	T2,T4,T5

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T17
1	0	Covered	T2,T4,T5
1	1	Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T16,T17
1	1	1	Covered	T13,T16,T17

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T16,T17

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T13,T16,T17

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T13,T16,T17

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T17
1	0	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T9
1	1	0	Covered	T13,T16,T17
1	1	1	Covered	T2,T4,T5

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T2,T4,T5
1	1	Covered	T13,T16,T17

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T16,T17

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T17
1	0	Covered	T2,T4,T5
1	1	Covered	T13,T16,T17

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T13,T14,T15

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T15

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T9
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T17
1	1	Covered	T2,T4,T5

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		29	26	89.66
TERNARY	138	2	2	100.00
TERNARY	328	2	2	100.00
TERNARY	334	3	2	66.67
TERNARY	379	2	2	100.00
TERNARY	502	2	2	100.00
IF	124	3	2	66.67
IF	268	4	3	75.00
IF	288	3	3	100.00
IF	349	2	2	100.00
IF	412	2	2	100.00
IF	424	2	2	100.00
IF	480	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	328	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	334	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	379	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	502	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	124	if ((!rst_ni))
-2-:	126	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if (reqfifo_rvalid)
-2-:	269	if (reqfifo_rdata.error)
-3-:	272	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T13,T16,T17
1	0	1	Covered	T2,T4,T5
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if (reqfifo_rvalid)
-2-:	289	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T5
1	0	Covered	T13,T16,T17
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	412	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	424	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	480	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	185475583	185307285	0	0
DataIntgOptions_A	318	318	0	0
ReqOutKnown_A	185475583	185307285	0	0
SramDwHasByteGranularity_A	318	318	0	0
SramDwIsMultipleOfTlulWidth_A	318	318	0	0
TlOutKnownIfFifoKnown_A	185475583	185307285	0	0
TlOutValidKnown_A	185475583	185307285	0	0
WdataOutKnown_A	185475583	185307285	0	0
WeOutKnown_A	185475583	185307285	0	0
WmaskOutKnown_A	185475583	185307285	0	0
adapterNoReadOrWrite	318	318	0	0
rvalidHighReqFifoEmpty	185475583	38865	0	0
rvalidHighWhenRspFifoFull	185475583	38865	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	185307285	0	0
T1	8323	8258	0	0
T2	32271	32212	0	0
T3	181214	181128	0	0
T4	116986	116835	0	0
T5	840353	839942	0	0
T6	18198	18071	0	0
T7	311206	311060	0	0
T8	42285	42219	0	0
T9	547963	547621	0	0
T10	213073	212987	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318	318	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	185307285	0	0
T1	8323	8258	0	0
T2	32271	32212	0	0
T3	181214	181128	0	0
T4	116986	116835	0	0
T5	840353	839942	0	0
T6	18198	18071	0	0
T7	311206	311060	0	0
T8	42285	42219	0	0
T9	547963	547621	0	0
T10	213073	212987	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318	318	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318	318	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	185307285	0	0
T1	8323	8258	0	0
T2	32271	32212	0	0
T3	181214	181128	0	0
T4	116986	116835	0	0
T5	840353	839942	0	0
T6	18198	18071	0	0
T7	311206	311060	0	0
T8	42285	42219	0	0
T9	547963	547621	0	0
T10	213073	212987	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	185307285	0	0
T1	8323	8258	0	0
T2	32271	32212	0	0
T3	181214	181128	0	0
T4	116986	116835	0	0
T5	840353	839942	0	0
T6	18198	18071	0	0
T7	311206	311060	0	0
T8	42285	42219	0	0
T9	547963	547621	0	0
T10	213073	212987	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	185307285	0	0
T1	8323	8258	0	0
T2	32271	32212	0	0
T3	181214	181128	0	0
T4	116986	116835	0	0
T5	840353	839942	0	0
T6	18198	18071	0	0
T7	311206	311060	0	0
T8	42285	42219	0	0
T9	547963	547621	0	0
T10	213073	212987	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	185307285	0	0
T1	8323	8258	0	0
T2	32271	32212	0	0
T3	181214	181128	0	0
T4	116986	116835	0	0
T5	840353	839942	0	0
T6	18198	18071	0	0
T7	311206	311060	0	0
T8	42285	42219	0	0
T9	547963	547621	0	0
T10	213073	212987	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	185307285	0	0
T1	8323	8258	0	0
T2	32271	32212	0	0
T3	181214	181128	0	0
T4	116986	116835	0	0
T5	840353	839942	0	0
T6	18198	18071	0	0
T7	311206	311060	0	0
T8	42285	42219	0	0
T9	547963	547621	0	0
T10	213073	212987	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	318	318	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	38865	0	0
T2	32271	80	0	0
T3	181214	0	0	0
T4	116986	73	0	0
T5	840353	128	0	0
T6	18198	48	0	0
T7	311206	75	0	0
T8	42285	131	0	0
T9	547963	135	0	0
T10	213073	298	0	0
T11	845833	191	0	0
T12	0	93	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	185475583	38865	0	0
T2	32271	80	0	0
T3	181214	0	0	0
T4	116986	73	0	0
T5	840353	128	0	0
T6	18198	48	0	0
T7	311206	75	0	0
T8	42285	131	0	0
T9	547963	135	0	0
T10	213073	298	0	0
T11	845833	191	0	0
T12	0	93	0	0