Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 74041 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1974029 1 T2 14 T4 16 T5 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 531114 1 T2 134 T4 158 T5 86
values[0x0] 744425 1 T23 91251 T24 55442 T25 11609
values[0x1] 772531 1 T23 94727 T24 57535 T25 11849



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 38736 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2009334 1 T2 86 T4 88 T5 54



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 7333 1 T86 1 T11 1 T12 2
valid_sources[0x01] 7682 1 T18 13 T116 2 T118 2
valid_sources[0x02] 6904 1 T116 2 T118 4 T133 2
valid_sources[0x03] 7265 1 T2 16 T18 15 T21 1
valid_sources[0x04] 8463 1 T118 1 T133 3 T134 1
valid_sources[0x05] 7375 1 T5 1 T10 36 T21 1
valid_sources[0x06] 7384 1 T4 70 T19 4 T21 1
valid_sources[0x07] 7914 1 T5 1 T18 2 T118 4
valid_sources[0x08] 7753 1 T5 1 T118 3 T21 2
valid_sources[0x09] 8238 1 T5 1 T18 1 T118 4
valid_sources[0x0a] 8086 1 T5 2 T116 1 T118 10
valid_sources[0x0b] 8975 1 T18 1 T118 3 T86 1
valid_sources[0x0c] 8700 1 T116 1 T135 10 T88 1
valid_sources[0x0d] 6819 1 T5 1 T18 6 T118 2
valid_sources[0x0e] 7989 1 T6 4 T116 1 T11 1
valid_sources[0x0f] 6545 1 T86 2 T11 1 T136 2
valid_sources[0x10] 6604 1 T18 3 T118 3 T21 2
valid_sources[0x11] 8412 1 T5 1 T18 4 T119 4
valid_sources[0x12] 7921 1 T5 1 T116 1 T118 1
valid_sources[0x13] 7812 1 T136 5 T133 3 T134 1
valid_sources[0x14] 10006 1 T18 5 T21 1 T11 1
valid_sources[0x15] 7103 1 T116 2 T118 1 T119 1
valid_sources[0x16] 9001 1 T118 1 T137 1 T134 1
valid_sources[0x17] 9808 1 T18 9 T11 1 T138 2
valid_sources[0x18] 8568 1 T118 2 T119 2 T21 2
valid_sources[0x19] 6666 1 T118 1 T137 1 T139 35
valid_sources[0x1a] 9116 1 T5 1 T18 1 T118 1
valid_sources[0x1b] 8009 1 T5 1 T118 1 T21 3
valid_sources[0x1c] 7305 1 T116 1 T118 2 T11 1
valid_sources[0x1d] 9275 1 T116 2 T117 22 T118 1
valid_sources[0x1e] 8143 1 T5 1 T116 1 T134 1
valid_sources[0x1f] 7480 1 T18 4 T134 1 T140 3
valid_sources[0x20] 7621 1 T116 1 T119 2 T21 1
valid_sources[0x21] 8381 1 T137 1 T87 4 T88 2
valid_sources[0x22] 8827 1 T18 1 T116 2 T118 1
valid_sources[0x23] 8569 1 T5 1 T137 1 T87 1
valid_sources[0x24] 7366 1 T18 10 T118 1 T119 1
valid_sources[0x25] 7579 1 T17 2 T118 1 T21 3
valid_sources[0x26] 9696 1 T5 1 T86 1 T138 1
valid_sources[0x27] 9472 1 T18 14 T116 2 T118 3
valid_sources[0x28] 9136 1 T118 2 T21 1 T137 2
valid_sources[0x29] 7811 1 T21 1 T137 4 T12 7
valid_sources[0x2a] 7762 1 T118 1 T119 1 T21 1
valid_sources[0x2b] 8199 1 T5 3 T118 1 T119 1
valid_sources[0x2c] 8144 1 T118 4 T11 1 T137 2
valid_sources[0x2d] 8435 1 T19 1 T118 2 T119 1
valid_sources[0x2e] 7813 1 T5 1 T18 1 T119 1
valid_sources[0x2f] 7716 1 T116 1 T21 1 T137 1
valid_sources[0x30] 7087 1 T118 1 T87 3 T12 2
valid_sources[0x31] 7208 1 T118 1 T137 2 T12 1
valid_sources[0x32] 9186 1 T13 2 T21 3 T86 1
valid_sources[0x33] 7350 1 T116 2 T21 1 T137 4
valid_sources[0x34] 8185 1 T5 1 T118 1 T119 1
valid_sources[0x35] 7477 1 T116 1 T118 1 T21 6
valid_sources[0x36] 8359 1 T21 4 T86 1 T11 2
valid_sources[0x37] 7007 1 T5 1 T6 12 T18 1
valid_sources[0x38] 7496 1 T18 5 T13 1 T118 7
valid_sources[0x39] 7568 1 T119 3 T86 1 T48 1
valid_sources[0x3a] 7876 1 T5 1 T116 1 T118 3
valid_sources[0x3b] 9852 1 T5 1 T18 4 T118 3
valid_sources[0x3c] 7731 1 T118 1 T135 10 T87 2
valid_sources[0x3d] 8069 1 T118 1 T21 1 T137 1
valid_sources[0x3e] 7734 1 T18 2 T116 1 T118 1
valid_sources[0x3f] 7653 1 T6 3 T18 17 T116 2
valid_sources[0x40] 7846 1 T18 1 T15 3 T118 6
valid_sources[0x41] 9136 1 T13 3 T118 1 T11 1
valid_sources[0x42] 8081 1 T5 1 T12 1 T133 1
valid_sources[0x43] 7927 1 T19 1 T139 10 T88 10
valid_sources[0x44] 6354 1 T19 6 T116 1 T118 1
valid_sources[0x45] 10661 1 T4 21 T119 5 T12 1
valid_sources[0x46] 7327 1 T118 2 T21 3 T12 2
valid_sources[0x47] 7474 1 T2 51 T5 1 T18 2
valid_sources[0x48] 10570 1 T118 1 T21 1 T86 1
valid_sources[0x49] 9200 1 T5 1 T116 1 T118 1
valid_sources[0x4a] 8784 1 T118 6 T86 1 T134 4
valid_sources[0x4b] 7191 1 T5 1 T116 1 T133 2
valid_sources[0x4c] 8409 1 T6 6 T10 19 T18 8
valid_sources[0x4d] 8455 1 T118 3 T21 2 T137 2
valid_sources[0x4e] 7894 1 T18 1 T19 10 T86 1
valid_sources[0x4f] 9685 1 T5 1 T116 1 T118 4
valid_sources[0x50] 10249 1 T4 23 T11 1 T137 3
valid_sources[0x51] 8457 1 T116 1 T119 1 T21 1
valid_sources[0x52] 7983 1 T116 1 T118 2 T21 3
valid_sources[0x53] 6827 1 T5 1 T18 2 T118 1
valid_sources[0x54] 6946 1 T18 9 T116 1 T118 3
valid_sources[0x55] 7323 1 T5 1 T21 4 T137 5
valid_sources[0x56] 6722 1 T5 1 T118 1 T21 2
valid_sources[0x57] 7110 1 T18 4 T118 3 T11 1
valid_sources[0x58] 8676 1 T18 10 T116 1 T118 3
valid_sources[0x59] 7233 1 T116 1 T21 2 T86 1
valid_sources[0x5a] 9325 1 T116 1 T118 1 T21 4
valid_sources[0x5b] 7482 1 T5 1 T116 4 T119 2
valid_sources[0x5c] 8657 1 T5 1 T118 3 T21 2
valid_sources[0x5d] 8974 1 T118 1 T119 3 T21 1
valid_sources[0x5e] 9393 1 T116 1 T118 1 T119 2
valid_sources[0x5f] 6795 1 T5 1 T18 2 T11 1
valid_sources[0x60] 9677 1 T116 3 T137 2 T136 1
valid_sources[0x61] 7682 1 T18 18 T137 4 T138 5
valid_sources[0x62] 7405 1 T5 1 T118 3 T137 1
valid_sources[0x63] 7645 1 T19 5 T116 1 T21 1
valid_sources[0x64] 7105 1 T19 1 T116 1 T118 3
valid_sources[0x65] 8058 1 T5 1 T19 4 T140 1
valid_sources[0x66] 7818 1 T88 3 T133 2 T134 1
valid_sources[0x67] 7437 1 T137 1 T138 1 T133 2
valid_sources[0x68] 8349 1 T21 1 T86 1 T11 2
valid_sources[0x69] 7604 1 T4 23 T5 2 T18 1
valid_sources[0x6a] 7224 1 T18 5 T116 2 T117 28
valid_sources[0x6b] 7712 1 T118 1 T119 3 T137 1
valid_sources[0x6c] 7365 1 T5 1 T116 1 T118 3
valid_sources[0x6d] 7987 1 T118 1 T21 1 T11 1
valid_sources[0x6e] 8555 1 T18 12 T86 1 T12 1
valid_sources[0x6f] 8070 1 T18 1 T117 37 T86 1
valid_sources[0x70] 8360 1 T18 13 T118 2 T88 4
valid_sources[0x71] 7111 1 T5 1 T19 1 T21 4
valid_sources[0x72] 8200 1 T118 6 T21 1 T86 1
valid_sources[0x73] 7507 1 T18 6 T116 2 T118 3
valid_sources[0x74] 9893 1 T21 1 T137 4 T138 1
valid_sources[0x75] 7337 1 T119 1 T138 1 T88 3
valid_sources[0x76] 9254 1 T119 1 T86 1 T11 3
valid_sources[0x77] 6858 1 T18 9 T118 2 T21 2
valid_sources[0x78] 8483 1 T5 1 T118 1 T119 3
valid_sources[0x79] 9976 1 T2 10 T5 2 T18 10
valid_sources[0x7a] 7918 1 T116 1 T21 1 T29 1
valid_sources[0x7b] 8631 1 T5 3 T18 7 T15 6
valid_sources[0x7c] 7268 1 T86 1 T137 4 T12 2
valid_sources[0x7d] 8892 1 T6 1 T18 7 T118 1
valid_sources[0x7e] 7844 1 T137 1 T138 3 T88 2
valid_sources[0x7f] 10174 1 T5 2 T18 2 T118 4
valid_sources[0x80] 6616 1 T6 3 T86 1 T11 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 496268 1 T2 14 T4 16 T5 8
values[0x0] all_enables biggest_size 738027 1 T23 90509 T24 54954 T25 11489
values[0x1] all_enables biggest_size 739734 1 T23 90705 T24 55058 T25 11313


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 145416 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1483109 1 T1 1 T2 28 T3 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 404642 1 T1 1 T2 64 T3 1
values[0x0] 565844 1 T8 3 T9 7 T35 11
values[0x1] 658039 1 T8 6 T9 6 T35 8



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 64655 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1563870 1 T1 1 T2 33 T3 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 6527 1 T137 3 T88 2 T91 2
valid_sources[0x01] 5789 1 T2 1 T17 3 T135 3
valid_sources[0x02] 5354 1 T14 1 T22 1 T137 1
valid_sources[0x03] 5820 1 T76 1 T88 2 T91 2
valid_sources[0x04] 6916 1 T22 1 T135 1 T29 1
valid_sources[0x05] 6612 1 T2 1 T19 1 T137 1
valid_sources[0x06] 6403 1 T137 1 T49 1 T141 1
valid_sources[0x07] 7174 1 T2 1 T5 2 T29 1
valid_sources[0x08] 5807 1 T5 2 T19 1 T22 1
valid_sources[0x09] 6240 1 T2 1 T91 1 T23 986
valid_sources[0x0a] 6889 1 T88 2 T23 923 T24 237
valid_sources[0x0b] 6090 1 T47 2 T89 1 T91 2
valid_sources[0x0c] 6195 1 T135 1 T29 1 T23 1030
valid_sources[0x0d] 6168 1 T142 1 T23 967 T24 357
valid_sources[0x0e] 5406 1 T137 1 T23 14 T24 463
valid_sources[0x0f] 5791 1 T90 1 T23 323 T24 479
valid_sources[0x10] 6744 1 T143 3 T144 2 T23 1247
valid_sources[0x11] 6418 1 T14 1 T137 1 T145 1
valid_sources[0x12] 8944 1 T88 3 T89 1 T23 2261
valid_sources[0x13] 6680 1 T88 1 T92 1 T23 436
valid_sources[0x14] 6595 1 T22 1 T86 3 T23 1233
valid_sources[0x15] 6207 1 T5 1 T135 3 T146 1
valid_sources[0x16] 6392 1 T17 3 T72 1 T137 1
valid_sources[0x17] 7169 1 T135 2 T87 1 T132 1
valid_sources[0x18] 6711 1 T2 1 T137 1 T23 478
valid_sources[0x19] 6004 1 T5 1 T90 1 T91 1
valid_sources[0x1a] 6433 1 T87 2 T90 1 T91 1
valid_sources[0x1b] 5769 1 T17 3 T15 6 T23 375
valid_sources[0x1c] 6122 1 T2 1 T137 2 T91 1
valid_sources[0x1d] 5960 1 T91 2 T146 1 T147 32
valid_sources[0x1e] 5616 1 T2 1 T148 1 T135 1
valid_sources[0x1f] 7021 1 T137 1 T90 1 T144 1
valid_sources[0x20] 7392 1 T89 1 T23 1217 T24 777
valid_sources[0x21] 7102 1 T6 1 T35 1 T149 1
valid_sources[0x22] 6098 1 T76 1 T137 4 T87 1
valid_sources[0x23] 6485 1 T22 1 T135 1 T137 4
valid_sources[0x24] 7070 1 T150 1 T135 8 T137 3
valid_sources[0x25] 6758 1 T137 5 T145 3 T49 1
valid_sources[0x26] 5787 1 T137 2 T146 2 T23 416
valid_sources[0x27] 7130 1 T47 2 T23 1235 T24 528
valid_sources[0x28] 6643 1 T49 2 T23 711 T24 564
valid_sources[0x29] 7005 1 T88 1 T151 7 T23 731
valid_sources[0x2a] 6475 1 T14 1 T137 1 T87 1
valid_sources[0x2b] 5418 1 T19 1 T75 1 T23 267
valid_sources[0x2c] 5987 1 T88 1 T90 1 T23 751
valid_sources[0x2d] 6351 1 T29 1 T90 1 T152 1
valid_sources[0x2e] 6732 1 T2 1 T135 2 T137 1
valid_sources[0x2f] 6049 1 T9 3 T87 1 T146 3
valid_sources[0x30] 5823 1 T47 2 T90 1 T146 1
valid_sources[0x31] 6220 1 T6 1 T70 3 T86 4
valid_sources[0x32] 6941 1 T88 1 T23 1574 T24 212
valid_sources[0x33] 6845 1 T49 1 T152 1 T23 1113
valid_sources[0x34] 6490 1 T135 2 T86 1 T90 1
valid_sources[0x35] 5478 1 T23 862 T24 174 T60 2
valid_sources[0x36] 6373 1 T2 2 T137 2 T23 471
valid_sources[0x37] 6678 1 T135 1 T88 2 T146 2
valid_sources[0x38] 7333 1 T2 1 T135 2 T47 1
valid_sources[0x39] 5775 1 T17 2 T73 1 T92 1
valid_sources[0x3a] 5221 1 T5 1 T6 1 T48 29
valid_sources[0x3b] 6667 1 T135 1 T88 1 T23 634
valid_sources[0x3c] 6035 1 T22 1 T49 1 T144 3
valid_sources[0x3d] 6096 1 T35 4 T135 1 T29 1
valid_sources[0x3e] 5154 1 T8 1 T135 8 T47 1
valid_sources[0x3f] 6625 1 T19 1 T88 1 T90 1
valid_sources[0x40] 6101 1 T19 2 T90 1 T91 1
valid_sources[0x41] 5802 1 T6 1 T29 1 T88 1
valid_sources[0x42] 5594 1 T17 2 T15 3 T49 3
valid_sources[0x43] 5923 1 T137 1 T23 934 T24 156
valid_sources[0x44] 5923 1 T14 1 T47 1 T137 2
valid_sources[0x45] 7237 1 T88 1 T23 729 T24 955
valid_sources[0x46] 7193 1 T2 1 T6 3 T87 1
valid_sources[0x47] 6159 1 T2 1 T135 9 T86 1
valid_sources[0x48] 6959 1 T2 1 T5 1 T47 1
valid_sources[0x49] 5620 1 T16 1 T86 1 T137 2
valid_sources[0x4a] 7555 1 T2 1 T135 1 T23 660
valid_sources[0x4b] 6647 1 T5 1 T14 1 T135 1
valid_sources[0x4c] 6846 1 T91 2 T144 2 T23 840
valid_sources[0x4d] 6889 1 T143 6 T152 2 T141 1
valid_sources[0x4e] 6435 1 T49 1 T23 744 T24 156
valid_sources[0x4f] 5685 1 T137 1 T87 1 T146 3
valid_sources[0x50] 6649 1 T22 1 T23 1081 T24 189
valid_sources[0x51] 7109 1 T151 1 T23 1417 T24 538
valid_sources[0x52] 6593 1 T5 1 T153 1 T137 4
valid_sources[0x53] 8200 1 T5 1 T6 1 T29 1
valid_sources[0x54] 5652 1 T19 1 T49 1 T88 1
valid_sources[0x55] 6115 1 T5 1 T14 1 T23 845
valid_sources[0x56] 6374 1 T2 1 T29 1 T23 847
valid_sources[0x57] 7626 1 T23 2045 T24 802 T25 99
valid_sources[0x58] 7076 1 T87 1 T91 3 T92 1
valid_sources[0x59] 6767 1 T35 3 T119 32 T137 1
valid_sources[0x5a] 5928 1 T137 1 T23 179 T24 379
valid_sources[0x5b] 5897 1 T2 2 T47 1 T154 1
valid_sources[0x5c] 6862 1 T135 1 T29 1 T87 1
valid_sources[0x5d] 5697 1 T2 1 T17 2 T76 1
valid_sources[0x5e] 6621 1 T23 1522 T24 576 T25 112
valid_sources[0x5f] 5980 1 T19 1 T14 1 T11 32
valid_sources[0x60] 6096 1 T23 1331 T24 656 T60 1
valid_sources[0x61] 5959 1 T155 1 T146 2 T23 13
valid_sources[0x62] 7394 1 T23 1036 T24 756 T156 6
valid_sources[0x63] 5834 1 T74 1 T143 2 T141 1
valid_sources[0x64] 5520 1 T76 1 T135 5 T47 1
valid_sources[0x65] 6216 1 T26 1 T23 1102 T24 221
valid_sources[0x66] 5681 1 T2 1 T6 1 T8 1
valid_sources[0x67] 6185 1 T2 1 T6 1 T19 1
valid_sources[0x68] 6170 1 T20 1 T29 1 T88 1
valid_sources[0x69] 6909 1 T2 1 T16 3 T49 1
valid_sources[0x6a] 6192 1 T22 1 T88 1 T92 1
valid_sources[0x6b] 5863 1 T146 1 T151 3 T23 482
valid_sources[0x6c] 7056 1 T23 1341 T24 319 T157 1
valid_sources[0x6d] 5697 1 T88 1 T90 1 T91 2
valid_sources[0x6e] 5856 1 T13 6 T141 1 T23 783
valid_sources[0x6f] 6810 1 T49 1 T23 1245 T24 473
valid_sources[0x70] 6484 1 T29 1 T89 2 T146 1
valid_sources[0x71] 5895 1 T1 1 T2 1 T152 1
valid_sources[0x72] 6029 1 T2 1 T158 2 T29 1
valid_sources[0x73] 6151 1 T2 1 T35 4 T29 1
valid_sources[0x74] 6096 1 T89 1 T152 1 T23 777
valid_sources[0x75] 5901 1 T6 1 T159 16 T160 1
valid_sources[0x76] 7258 1 T2 1 T3 1 T29 2
valid_sources[0x77] 6390 1 T47 1 T137 1 T91 1
valid_sources[0x78] 5886 1 T5 1 T49 1 T91 1
valid_sources[0x79] 6232 1 T132 3 T23 1218 T24 454
valid_sources[0x7a] 6067 1 T23 682 T24 425 T25 94
valid_sources[0x7b] 6132 1 T137 1 T49 1 T161 2
valid_sources[0x7c] 5763 1 T146 1 T23 209 T24 344
valid_sources[0x7d] 4889 1 T35 5 T19 1 T75 2
valid_sources[0x7e] 5989 1 T135 3 T86 2 T47 1
valid_sources[0x7f] 6518 1 T2 2 T6 1 T135 4
valid_sources[0x80] 6834 1 T90 1 T23 402 T24 692



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 373861 1 T1 1 T2 28 T3 1
values[0x0] all_enables biggest_size 554275 1 T8 1 T35 3 T70 1
values[0x1] all_enables biggest_size 554973 1 T8 2 T9 3 T74 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%