Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3567184

1

T2

120

T4

142

T5

78

full_word

2301368

1

T2

14

T4

16

T5

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5868252	1			T2	134		T4	158		T5	86
auto[TlIntgErrCmd]	102	1			T64	13		T65	4		T66	4
auto[TlIntgErrData]	101	1			T64	2		T65	4		T66	3
auto[TlIntgErrBoth]	97	1			T64	5		T65	2		T66	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931273

1

T2

134

T4

158

T5

86

auto[1]

4937279

1

T23

602156

T24

367399

T25

77612

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	387135	1			T2	120		T4	142		T5	78
auto[TlIntgErrNone]	partial	auto[1]	3179780	1			T23	387167		T24	236812		T25	50407
auto[TlIntgErrNone]	full_word	auto[0]	543993	1			T2	14		T4	16		T5	8
auto[TlIntgErrNone]	full_word	auto[1]	1757344	1			T23	214989		T24	130587		T25	27205
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T64	5		T65	3		T66	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T64	7		T65	1		T66	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T128	1		T126	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T64	1		T128	1		T126	3
auto[TlIntgErrData]	partial	auto[0]	45	1			T123	1		T128	4		T129	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T64	2		T65	3		T66	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T65	1		T66	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T66	1		T129	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T65	2		T66	1		T123	4
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T64	5		T66	2		T128	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T128	1		T130	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T121	1		T131	1		T127	1