Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1410221

1

T1

6

T2

6

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	390206	1			T1	75		T2	6		T3	76
values[0x0]	532497	1			T14	22487		T15	25218		T16	44389
values[0x1]	552291	1			T14	22889		T15	26351		T16	46348

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33028	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1441966

1

T1

42

T2

6

T3

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7529	1			T11	1		T13	1		T14	268
valid_sources[0x01]	6470	1			T6	4		T7	1		T9	2
valid_sources[0x02]	5920	1			T13	2		T14	255		T60	1
valid_sources[0x03]	4531	1			T13	6		T14	212		T61	1
valid_sources[0x04]	6309	1			T7	2		T9	1		T11	1
valid_sources[0x05]	5132	1			T7	1		T9	1		T11	1
valid_sources[0x06]	5271	1			T1	2		T7	3		T13	1
valid_sources[0x07]	5936	1			T7	3		T11	3		T13	2
valid_sources[0x08]	5024	1			T7	2		T13	2		T14	203
valid_sources[0x09]	5465	1			T7	1		T11	2		T13	1
valid_sources[0x0a]	5153	1			T1	3		T7	2		T11	1
valid_sources[0x0b]	6621	1			T6	1		T7	2		T11	1
valid_sources[0x0c]	5770	1			T7	2		T12	16		T13	1
valid_sources[0x0d]	5615	1			T1	1		T6	1		T14	177
valid_sources[0x0e]	6171	1			T7	2		T9	1		T11	1
valid_sources[0x0f]	5649	1			T1	1		T4	71		T6	3
valid_sources[0x10]	5965	1			T2	2		T6	1		T7	1
valid_sources[0x11]	6323	1			T6	1		T13	2		T14	202
valid_sources[0x12]	5043	1			T1	1		T6	1		T11	2
valid_sources[0x13]	6286	1			T1	1		T6	1		T7	4
valid_sources[0x14]	6477	1			T7	2		T11	1		T13	2
valid_sources[0x15]	5117	1			T6	3		T13	1		T14	273
valid_sources[0x16]	5220	1			T9	1		T11	1		T13	1
valid_sources[0x17]	6758	1			T9	1		T13	1		T14	202
valid_sources[0x18]	4999	1			T2	1		T7	1		T11	1
valid_sources[0x19]	6366	1			T1	1		T9	1		T11	2
valid_sources[0x1a]	4354	1			T3	4		T6	2		T7	2
valid_sources[0x1b]	5855	1			T7	3		T14	230		T63	2
valid_sources[0x1c]	6378	1			T9	1		T13	2		T14	192
valid_sources[0x1d]	6400	1			T6	2		T11	2		T14	237
valid_sources[0x1e]	6067	1			T6	3		T7	2		T11	1
valid_sources[0x1f]	5844	1			T7	1		T11	1		T13	3
valid_sources[0x20]	4557	1			T7	1		T11	5		T14	254
valid_sources[0x21]	5470	1			T7	2		T11	2		T13	1
valid_sources[0x22]	7022	1			T11	5		T13	2		T14	238
valid_sources[0x23]	5092	1			T7	1		T9	1		T11	1
valid_sources[0x24]	5183	1			T7	1		T12	29		T13	1
valid_sources[0x25]	5696	1			T7	1		T11	1		T14	234
valid_sources[0x26]	6309	1			T1	2		T3	14		T7	5
valid_sources[0x27]	4480	1			T3	1		T9	1		T11	3
valid_sources[0x28]	5332	1			T6	1		T9	2		T14	222
valid_sources[0x29]	6189	1			T1	1		T7	2		T11	1
valid_sources[0x2a]	6975	1			T7	3		T13	3		T14	228
valid_sources[0x2b]	6605	1			T6	1		T11	3		T13	1
valid_sources[0x2c]	5373	1			T7	2		T13	1		T14	241
valid_sources[0x2d]	6626	1			T6	3		T7	3		T9	1
valid_sources[0x2e]	6219	1			T4	15		T7	3		T13	1
valid_sources[0x2f]	5752	1			T1	2		T11	4		T14	198
valid_sources[0x30]	6715	1			T6	1		T7	2		T9	2
valid_sources[0x31]	4434	1			T1	1		T7	1		T11	1
valid_sources[0x32]	5858	1			T7	4		T13	2		T14	235
valid_sources[0x33]	5939	1			T7	4		T9	1		T14	257
valid_sources[0x34]	5752	1			T1	1		T7	2		T13	2
valid_sources[0x35]	5375	1			T11	2		T14	282		T61	2
valid_sources[0x36]	5474	1			T6	4		T11	3		T13	1
valid_sources[0x37]	5528	1			T6	2		T7	5		T11	3
valid_sources[0x38]	6639	1			T6	3		T7	2		T11	1
valid_sources[0x39]	5359	1			T7	1		T9	1		T11	3
valid_sources[0x3a]	5128	1			T6	3		T7	1		T11	2
valid_sources[0x3b]	7277	1			T6	4		T7	1		T11	2
valid_sources[0x3c]	5145	1			T9	1		T11	1		T14	294
valid_sources[0x3d]	6222	1			T1	1		T6	1		T7	2
valid_sources[0x3e]	5761	1			T9	2		T14	194		T60	1
valid_sources[0x3f]	6911	1			T1	1		T6	8		T7	2
valid_sources[0x40]	5363	1			T6	4		T7	3		T14	270
valid_sources[0x41]	5427	1			T7	1		T11	2		T14	214
valid_sources[0x42]	7043	1			T1	1		T7	1		T11	2
valid_sources[0x43]	4799	1			T7	2		T9	1		T11	2
valid_sources[0x44]	5272	1			T7	3		T13	2		T14	160
valid_sources[0x45]	4641	1			T7	2		T11	2		T14	226
valid_sources[0x46]	5955	1			T1	2		T7	2		T13	1
valid_sources[0x47]	5230	1			T7	2		T11	2		T13	1
valid_sources[0x48]	6290	1			T1	2		T6	1		T7	1
valid_sources[0x49]	5018	1			T7	4		T9	1		T11	5
valid_sources[0x4a]	6304	1			T1	1		T7	1		T11	1
valid_sources[0x4b]	5453	1			T1	2		T7	2		T9	1
valid_sources[0x4c]	5298	1			T7	8		T13	1		T14	235
valid_sources[0x4d]	5835	1			T1	2		T9	1		T11	1
valid_sources[0x4e]	5625	1			T11	3		T13	1		T14	216
valid_sources[0x4f]	6532	1			T7	1		T9	1		T11	2
valid_sources[0x50]	5275	1			T11	2		T13	1		T14	201
valid_sources[0x51]	6596	1			T6	2		T7	1		T13	1
valid_sources[0x52]	5722	1			T6	2		T7	1		T9	1
valid_sources[0x53]	5774	1			T1	1		T2	1		T4	43
valid_sources[0x54]	5481	1			T6	2		T7	2		T11	2
valid_sources[0x55]	5382	1			T6	3		T7	1		T11	3
valid_sources[0x56]	5307	1			T2	1		T6	1		T7	1
valid_sources[0x57]	6496	1			T6	5		T7	2		T9	1
valid_sources[0x58]	4944	1			T6	3		T7	2		T11	1
valid_sources[0x59]	6371	1			T6	2		T7	1		T11	1
valid_sources[0x5a]	5731	1			T3	1		T7	3		T9	1
valid_sources[0x5b]	5171	1			T7	1		T13	3		T14	300
valid_sources[0x5c]	6426	1			T7	1		T11	1		T14	222
valid_sources[0x5d]	5277	1			T7	3		T9	2		T11	1
valid_sources[0x5e]	4500	1			T3	2		T6	1		T11	1
valid_sources[0x5f]	5254	1			T6	2		T11	2		T13	3
valid_sources[0x60]	5190	1			T6	5		T7	2		T11	4
valid_sources[0x61]	6051	1			T1	1		T6	2		T7	1
valid_sources[0x62]	5086	1			T7	2		T11	1		T14	250
valid_sources[0x63]	5622	1			T1	1		T7	1		T14	171
valid_sources[0x64]	7043	1			T7	2		T14	172		T60	3
valid_sources[0x65]	5003	1			T7	1		T11	3		T14	276
valid_sources[0x66]	6052	1			T6	2		T7	4		T9	1
valid_sources[0x67]	5437	1			T7	3		T14	267		T61	1
valid_sources[0x68]	7492	1			T1	1		T6	4		T7	2
valid_sources[0x69]	5792	1			T1	1		T6	1		T11	2
valid_sources[0x6a]	5205	1			T6	2		T13	2		T14	302
valid_sources[0x6b]	5147	1			T6	6		T7	1		T13	2
valid_sources[0x6c]	6596	1			T7	1		T9	1		T11	3
valid_sources[0x6d]	6004	1			T6	1		T7	1		T14	172
valid_sources[0x6e]	5646	1			T4	21		T6	6		T7	1
valid_sources[0x6f]	6089	1			T9	1		T11	1		T13	1
valid_sources[0x70]	6182	1			T1	1		T6	1		T7	1
valid_sources[0x71]	5977	1			T1	2		T13	2		T14	249
valid_sources[0x72]	5400	1			T7	2		T9	1		T11	1
valid_sources[0x73]	6058	1			T3	12		T7	1		T11	2
valid_sources[0x74]	6030	1			T6	2		T7	1		T13	2
valid_sources[0x75]	6500	1			T7	1		T11	2		T13	1
valid_sources[0x76]	5643	1			T1	3		T7	1		T9	1
valid_sources[0x77]	4820	1			T6	8		T7	3		T11	2
valid_sources[0x78]	5262	1			T1	1		T11	1		T13	1
valid_sources[0x79]	4836	1			T7	2		T13	2		T14	214
valid_sources[0x7a]	6243	1			T6	2		T9	1		T13	1
valid_sources[0x7b]	5911	1			T7	2		T13	2		T14	243
valid_sources[0x7c]	5539	1			T6	5		T11	2		T13	1
valid_sources[0x7d]	5430	1			T4	19		T7	1		T11	4
valid_sources[0x7e]	4944	1			T7	2		T11	3		T13	1
valid_sources[0x7f]	6079	1			T6	6		T7	1		T11	3
valid_sources[0x80]	6018	1			T1	1		T6	5		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

354198

1

T1

6

T2

6

T3

6

values[0x0]

all_enables

biggest_size

527762

1

T14

22310

T15

25017

T16

44020

values[0x1]

all_enables

biggest_size

528261

1

T14

21964

T15

25234

T16

44409

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	108271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1084262

1

T1

12

T2

12

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	299055	1			T1	32		T2	27		T3	32
values[0x0]	414574	1			T5	4		T14	16242		T15	19337
values[0x1]	478904	1			T5	7		T14	18356		T15	22714

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49581	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1142952

1

T1

17

T2

13

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4537	1			T14	16		T60	2		T83	2
valid_sources[0x01]	3721	1			T14	205		T15	175		T16	335
valid_sources[0x02]	4297	1			T14	169		T80	3		T83	1
valid_sources[0x03]	4664	1			T14	528		T15	225		T16	465
valid_sources[0x04]	4773	1			T14	237		T60	1		T82	1
valid_sources[0x05]	4516	1			T14	113		T15	270		T16	308
valid_sources[0x06]	3818	1			T5	1		T14	34		T80	1
valid_sources[0x07]	4857	1			T14	109		T62	1		T15	191
valid_sources[0x08]	4374	1			T14	140		T15	223		T16	484
valid_sources[0x09]	5292	1			T14	149		T81	5		T15	181
valid_sources[0x0a]	4300	1			T3	1		T14	15		T15	191
valid_sources[0x0b]	4602	1			T14	69		T83	1		T15	144
valid_sources[0x0c]	4902	1			T14	368		T15	215		T16	381
valid_sources[0x0d]	5187	1			T14	249		T15	245		T37	10
valid_sources[0x0e]	4929	1			T14	438		T83	1		T15	245
valid_sources[0x0f]	5313	1			T3	1		T14	369		T15	214
valid_sources[0x10]	5538	1			T14	125		T15	269		T16	641
valid_sources[0x11]	3845	1			T14	141		T15	293		T16	574
valid_sources[0x12]	5413	1			T14	278		T15	276		T16	375
valid_sources[0x13]	4820	1			T14	576		T80	3		T15	179
valid_sources[0x14]	4872	1			T14	280		T82	1		T15	210
valid_sources[0x15]	4910	1			T9	3		T14	100		T80	17
valid_sources[0x16]	4009	1			T1	1		T14	171		T60	1
valid_sources[0x17]	4681	1			T1	2		T14	404		T30	1
valid_sources[0x18]	4952	1			T14	202		T60	1		T15	282
valid_sources[0x19]	3870	1			T3	1		T14	198		T15	179
valid_sources[0x1a]	4759	1			T1	2		T5	1		T9	4
valid_sources[0x1b]	4940	1			T14	68		T15	192		T16	235
valid_sources[0x1c]	4621	1			T14	351		T15	260		T16	121
valid_sources[0x1d]	4982	1			T14	132		T83	1		T15	236
valid_sources[0x1e]	4573	1			T14	334		T15	224		T16	344
valid_sources[0x1f]	3756	1			T14	419		T15	233		T16	131
valid_sources[0x20]	4674	1			T14	390		T15	237		T16	225
valid_sources[0x21]	5474	1			T14	182		T15	228		T16	637
valid_sources[0x22]	4977	1			T14	20		T82	1		T15	207
valid_sources[0x23]	4565	1			T14	49		T60	1		T15	185
valid_sources[0x24]	4339	1			T1	1		T14	154		T15	187
valid_sources[0x25]	4590	1			T9	1		T14	330		T15	203
valid_sources[0x26]	4318	1			T14	165		T83	2		T15	202
valid_sources[0x27]	5099	1			T14	14		T83	1		T15	226
valid_sources[0x28]	4663	1			T14	153		T63	2		T15	167
valid_sources[0x29]	5650	1			T14	328		T15	170		T16	174
valid_sources[0x2a]	5205	1			T14	228		T15	199		T16	358
valid_sources[0x2b]	4782	1			T14	52		T15	242		T16	323
valid_sources[0x2c]	5867	1			T14	182		T80	4		T15	213
valid_sources[0x2d]	5698	1			T1	1		T14	526		T15	208
valid_sources[0x2e]	4941	1			T14	57		T59	1		T15	200
valid_sources[0x2f]	4089	1			T14	19		T15	181		T16	624
valid_sources[0x30]	4145	1			T14	16		T15	294		T16	242
valid_sources[0x31]	4376	1			T3	1		T14	114		T132	96
valid_sources[0x32]	5070	1			T14	182		T15	265		T16	624
valid_sources[0x33]	4301	1			T14	14		T28	2		T15	173
valid_sources[0x34]	4532	1			T14	7		T80	10		T15	218
valid_sources[0x35]	4018	1			T14	5		T15	230		T16	20
valid_sources[0x36]	5415	1			T14	488		T80	1		T82	1
valid_sources[0x37]	5172	1			T14	523		T15	243		T16	200
valid_sources[0x38]	4040	1			T14	113		T15	195		T16	470
valid_sources[0x39]	4813	1			T14	410		T82	1		T15	214
valid_sources[0x3a]	4577	1			T14	22		T60	1		T15	243
valid_sources[0x3b]	4096	1			T14	175		T80	1		T83	2
valid_sources[0x3c]	5011	1			T14	313		T15	188		T16	393
valid_sources[0x3d]	4357	1			T14	61		T15	175		T133	1
valid_sources[0x3e]	4130	1			T14	119		T15	291		T16	121
valid_sources[0x3f]	4061	1			T5	1		T14	104		T80	2
valid_sources[0x40]	4918	1			T14	307		T63	4		T15	237
valid_sources[0x41]	5504	1			T14	108		T30	7		T15	263
valid_sources[0x42]	5265	1			T14	197		T15	281		T16	638
valid_sources[0x43]	4932	1			T14	186		T15	216		T16	572
valid_sources[0x44]	5080	1			T1	2		T14	33		T15	198
valid_sources[0x45]	4284	1			T14	123		T15	226		T16	524
valid_sources[0x46]	4078	1			T14	61		T15	276		T16	652
valid_sources[0x47]	3476	1			T14	18		T82	1		T15	234
valid_sources[0x48]	5078	1			T1	1		T14	245		T59	13
valid_sources[0x49]	5145	1			T3	1		T14	322		T15	216
valid_sources[0x4a]	4575	1			T14	12		T15	193		T16	409
valid_sources[0x4b]	4029	1			T14	85		T15	232		T16	514
valid_sources[0x4c]	4429	1			T3	1		T14	130		T82	1
valid_sources[0x4d]	4385	1			T9	1		T14	312		T60	1
valid_sources[0x4e]	4022	1			T14	120		T15	292		T16	318
valid_sources[0x4f]	4780	1			T14	87		T15	198		T16	164
valid_sources[0x50]	4664	1			T1	2		T14	33		T15	223
valid_sources[0x51]	4454	1			T14	237		T15	193		T16	394
valid_sources[0x52]	4909	1			T14	6		T80	2		T15	246
valid_sources[0x53]	5344	1			T9	2		T10	1		T14	389
valid_sources[0x54]	4559	1			T14	174		T15	182		T16	403
valid_sources[0x55]	6149	1			T14	109		T15	223		T16	754
valid_sources[0x56]	5256	1			T14	21		T80	3		T15	223
valid_sources[0x57]	3885	1			T8	1		T14	16		T59	9
valid_sources[0x58]	5126	1			T14	121		T60	1		T81	3
valid_sources[0x59]	3154	1			T3	1		T14	12		T15	191
valid_sources[0x5a]	3697	1			T14	189		T15	224		T16	177
valid_sources[0x5b]	5321	1			T6	96		T14	51		T83	2
valid_sources[0x5c]	5754	1			T14	107		T15	219		T16	1070
valid_sources[0x5d]	4795	1			T14	247		T80	8		T15	212
valid_sources[0x5e]	4538	1			T14	25		T62	3		T83	2
valid_sources[0x5f]	4423	1			T14	120		T15	185		T16	427
valid_sources[0x60]	5252	1			T5	1		T9	3		T14	346
valid_sources[0x61]	4239	1			T3	1		T14	195		T15	210
valid_sources[0x62]	4422	1			T14	67		T15	217		T16	200
valid_sources[0x63]	5008	1			T9	1		T14	77		T15	209
valid_sources[0x64]	4903	1			T14	131		T80	13		T15	228
valid_sources[0x65]	5318	1			T14	27		T82	1		T15	242
valid_sources[0x66]	5364	1			T14	257		T15	229		T16	282
valid_sources[0x67]	5811	1			T14	399		T28	3		T15	210
valid_sources[0x68]	3966	1			T5	1		T14	312		T15	187
valid_sources[0x69]	4204	1			T3	1		T14	218		T62	28
valid_sources[0x6a]	4728	1			T3	1		T14	26		T15	292
valid_sources[0x6b]	3074	1			T14	73		T15	250		T16	249
valid_sources[0x6c]	4100	1			T1	2		T14	85		T15	214
valid_sources[0x6d]	4286	1			T14	22		T80	12		T15	174
valid_sources[0x6e]	4932	1			T14	152		T15	181		T16	396
valid_sources[0x6f]	4277	1			T14	359		T80	17		T15	190
valid_sources[0x70]	4482	1			T14	452		T80	1		T15	235
valid_sources[0x71]	4312	1			T14	129		T15	218		T16	407
valid_sources[0x72]	4845	1			T14	108		T15	206		T16	247
valid_sources[0x73]	3702	1			T14	95		T15	224		T16	24
valid_sources[0x74]	4799	1			T14	7		T60	1		T82	4
valid_sources[0x75]	4399	1			T1	1		T9	2		T14	302
valid_sources[0x76]	5005	1			T14	360		T80	2		T15	233
valid_sources[0x77]	5330	1			T3	1		T14	363		T15	235
valid_sources[0x78]	3685	1			T14	74		T60	1		T82	1
valid_sources[0x79]	3943	1			T14	190		T15	149		T16	329
valid_sources[0x7a]	4005	1			T14	44		T28	1		T15	228
valid_sources[0x7b]	4106	1			T3	2		T14	136		T15	241
valid_sources[0x7c]	4954	1			T14	191		T15	209		T16	368
valid_sources[0x7d]	5435	1			T3	1		T14	383		T80	2
valid_sources[0x7e]	5091	1			T14	87		T60	1		T15	176
valid_sources[0x7f]	4016	1			T14	19		T15	183		T16	205
valid_sources[0x80]	5443	1			T14	363		T15	268		T16	290

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

273582

1

T1

12

T2

12

T3

14

values[0x0]

all_enables

biggest_size

405593

1

T5

3

T14

15909

T15

18927

values[0x1]

all_enables

biggest_size

405087

1

T14

15548

T15

19083

T37

1