Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2583563

1

T1

69

T3

70

T4

212

full_word

1645211

1

T1

6

T2

4

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4228484	1			T1	75		T2	4		T3	76
auto[TlIntgErrCmd]	100	1			T64	7		T65	7		T66	5
auto[TlIntgErrData]	86	1			T64	3		T65	5		T66	7
auto[TlIntgErrBoth]	104	1			T64	10		T65	8		T66	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675888

1

T1

75

T2

4

T3

76

auto[1]

3552886

1

T14

139797

T15

171026

T16

289378

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	287180	1			T1	69		T3	70		T4	212
auto[TlIntgErrNone]	partial	auto[1]	2296121	1			T14	88022		T15	111154		T16	184483
auto[TlIntgErrNone]	full_word	auto[0]	388575	1			T1	6		T2	4		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	1256608	1			T14	51775		T15	59872		T16	104895
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T64	3		T65	3		T66	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T64	4		T65	3		T66	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T122	1		T123	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T65	1		T118	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T64	1		T65	2		T66	4
auto[TlIntgErrData]	partial	auto[1]	37	1			T65	2		T66	3		T117	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T64	1		T65	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T64	1		T125	1		T126	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T64	6		T65	4		T66	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T64	3		T65	3		T66	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T65	1		T127	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T64	1		T118	2		T121	1