Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.58	96.97	93.59	97.88	100.00	99.02	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.68	91.60	86.28	99.07		96.47	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
212	1	1
258	1	1
313	1	1
414	8	8
415	8	8
417	8	8
418	8	8
420	8	8
421	8	8
425	1	1
427	1	1
430	1	1
431	1	1
432	1	1
433	1	1
438	1	1
442	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       212
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       258
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T30,T27
1	1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T34,T35,T36
1	0	Not Covered

 LINE       427
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T30,T27
1	0	Covered	T2,T8,T10

 LINE       438
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T37,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T37,T38

 LINE       442
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T30,T27
0	1	0	Covered	T2,T8,T10
1	0	0	Covered	T34,T35,T36

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T10,T11	Yes	T1,T11,T14	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T1,T11,T14	Yes	T1,T11,T14	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T5,T8	Yes	T2,T5,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T5,T8	Yes	T2,T5,T8	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	OUTPUT
kmac_data_i.error	No	Yes	T8,T10,T26	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T2,T6	Yes	T2,T6,T14	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T2,T6,T8	Yes	T2,T6,T9	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	212	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	195866140	195696753	0	0
BusRomIndicesMatch_A	195852509	195688846	0	0
FpvSecCmFifoRptrCheck_A	195866140	0	0	0
FpvSecCmFifoWptrCheck_A	195866140	0	0	0
FpvSecCmRegWeOnehotCheck_A	195866140	70	0	0
KeymgrDataODataKnown_A	195866140	55421370	0	0
KeymgrDataODataKnown_AKnownEnable	195866140	195696753	0	0
KeymgrDataOValidKnown_A	195866140	195696753	0	0
KeymgrValidChk_A	195866140	0	0	320
KmacDataODataKnown_A	195866140	140152200	0	0
KmacDataODataKnown_AKnownEnable	195866140	195696753	0	0
KmacDataOValidKnown_A	195866140	195696753	0	0
PwrmgrDataChk_A	195866140	0	0	320
PwrmgrDataOKnown_A	195866140	195696753	0	0
RegsTlOAReadyKnown_A	195866140	195696753	0	0
RegsTlODDataKnown_A	195866140	8033180	0	0
RegsTlODDataKnown_AKnownEnable	195866140	195696753	0	0
RegsTlODValidKnown_A	195866140	195696753	0	0
RomTlOAReadyKnown_A	195866140	195696753	0	0
RomTlODDataKnown_A	195866140	11738201	0	0
RomTlODDataKnown_AKnownEnable	195866140	195696753	0	0
RomTlODValidKnown_A	195866140	195696753	0	0
StabilityChkKmac_A	195866140	140149855	0	0
StabilityChkkeymgr_A	195866140	55420207	0	0
TlAccessChk_A	195866140	140275383	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	195866140	70	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	195866140	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	195866140	487	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	195866140	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195852509	195688846	0	0
T1	197108	196932	0	0
T2	291539	291289	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	70	0	0
T34	137258	10	0	0
T35	203558	20	0	0
T36	0	10	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	303526	0	0	0
T42	94831	0	0	0
T43	409145	0	0	0
T44	26240	0	0	0
T45	82804	0	0	0
T46	458249	0	0	0
T47	622010	0	0	0
T48	254172	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	55421370	0	0
T1	197108	1553	0	0
T2	291562	1463	0	0
T3	156982	1864	0	0
T4	179341	7355	0	0
T5	28908	31	0	0
T6	153641	5234	0	0
T7	9655	1388	0	0
T8	318194	134	0	0
T9	20311	2007	0	0
T10	196590	71	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	0	0	320

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	140152200	0	0
T1	197108	195246	0	0
T2	291562	290844	0	0
T3	156982	154810	0	0
T4	179341	171628	0	0
T5	28908	28710	0	0
T6	153641	147745	0	0
T7	9655	8184	0	0
T8	318194	317747	0	0
T9	20311	17805	0	0
T10	196590	196242	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	0	0	320

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	8033180	0	0
T1	197108	161	0	0
T2	291562	27	0	0
T3	156982	147	0	0
T4	179341	518	0	0
T5	28908	11	0	0
T6	153641	96	0	0
T7	9655	0	0	0
T8	318194	8	0	0
T9	20311	32	0	0
T10	196590	1	0	0
T14	0	643029	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	11738201	0	0
T1	197108	75	0	0
T2	291562	20	0	0
T3	156982	493	0	0
T4	179341	231	0	0
T5	28908	0	0	0
T6	153641	1375	0	0
T7	9655	390	0	0
T8	318194	0	0	0
T9	20311	403	0	0
T10	196590	0	0	0
T11	0	317	0	0
T12	0	57	0	0
T13	0	314	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	195696753	0	0
T1	197108	196932	0	0
T2	291562	291296	0	0
T3	156982	156836	0	0
T4	179341	179089	0	0
T5	28908	28821	0	0
T6	153641	153201	0	0
T7	9655	9593	0	0
T8	318194	318052	0	0
T9	20311	19860	0	0
T10	196590	196428	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	140149855	0	0
T1	197108	195244	0	0
T2	291562	290841	0	0
T3	156982	154808	0	0
T4	179341	171625	0	0
T5	28908	28709	0	0
T6	153641	147739	0	0
T7	9655	8183	0	0
T8	318194	317745	0	0
T9	20311	17800	0	0
T10	196590	196240	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	55420207	0	0
T1	197108	1551	0	0
T2	291562	1450	0	0
T3	156982	1862	0	0
T4	179341	7353	0	0
T5	28908	30	0	0
T6	153641	5230	0	0
T7	9655	1387	0	0
T8	318194	133	0	0
T9	20311	2005	0	0
T10	196590	70	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	140275383	0	0
T1	197108	195379	0	0
T2	291562	291150	0	0
T3	156982	154972	0	0
T4	179341	171734	0	0
T5	28908	28790	0	0
T6	153641	147967	0	0
T7	9655	8205	0	0
T8	318194	317918	0	0
T9	20311	17853	0	0
T10	196590	196357	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	70	0	0
T34	137258	10	0	0
T35	203558	20	0	0
T36	0	10	0	0
T39	0	20	0	0
T40	0	10	0	0
T41	303526	0	0	0
T42	94831	0	0	0
T43	409145	0	0	0
T44	26240	0	0	0
T45	82804	0	0	0
T46	458249	0	0	0
T47	622010	0	0	0
T48	254172	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	487	0	0
T2	291562	15	0	0
T3	156982	0	0	0
T4	179341	0	0	0
T5	28908	0	0	0
T6	153641	0	0	0
T7	9655	0	0	0
T8	318194	0	0	0
T9	20311	0	0	0
T10	196590	0	0	0
T11	168445	0	0	0
T27	0	15	0	0
T28	0	5	0	0
T29	0	10	0	0
T30	0	5	0	0
T49	0	5	0	0
T50	0	5	0	0
T51	0	5	0	0
T52	0	25	0	0
T53	0	10	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195866140	0	0	0