Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 77100 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1865668 1 T1 10 T4 10 T7 9



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 507786 1 T1 65 T4 98 T7 153
values[0x0] 705423 1 T16 77096 T17 19413 T18 18653
values[0x1] 729559 1 T16 80060 T17 19976 T18 19376



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 39807 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1902961 1 T1 38 T4 61 T7 100



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 7105 1 T8 1 T9 1 T38 1
valid_sources[0x01] 7593 1 T10 1 T61 5 T30 1
valid_sources[0x02] 7786 1 T4 3 T7 1 T8 2
valid_sources[0x03] 7584 1 T7 1 T10 1 T13 1
valid_sources[0x04] 7652 1 T7 1 T16 832 T53 1
valid_sources[0x05] 7443 1 T8 1 T61 2 T38 1
valid_sources[0x06] 8357 1 T10 1 T61 2 T16 814
valid_sources[0x07] 6867 1 T10 1 T11 18 T34 5
valid_sources[0x08] 8038 1 T1 3 T4 3 T7 1
valid_sources[0x09] 7385 1 T4 1 T8 1 T12 3
valid_sources[0x0a] 7357 1 T7 1 T10 1 T61 2
valid_sources[0x0b] 7731 1 T34 2 T46 2 T16 804
valid_sources[0x0c] 6771 1 T7 3 T9 2 T10 2
valid_sources[0x0d] 8750 1 T10 1 T61 3 T16 804
valid_sources[0x0e] 6925 1 T8 1 T16 794 T53 8
valid_sources[0x0f] 6644 1 T4 2 T10 2 T38 1
valid_sources[0x10] 7601 1 T7 1 T38 1 T103 2
valid_sources[0x11] 6963 1 T7 1 T10 1 T115 2
valid_sources[0x12] 6905 1 T10 1 T38 1 T16 815
valid_sources[0x13] 7260 1 T115 1 T16 839 T54 1
valid_sources[0x14] 7980 1 T4 1 T11 1 T16 821
valid_sources[0x15] 6862 1 T7 1 T16 796 T17 231
valid_sources[0x16] 7769 1 T7 2 T9 4 T10 1
valid_sources[0x17] 8544 1 T10 1 T61 2 T16 770
valid_sources[0x18] 7621 1 T4 1 T10 2 T34 3
valid_sources[0x19] 8506 1 T9 1 T10 1 T103 3
valid_sources[0x1a] 8576 1 T1 13 T10 2 T11 3
valid_sources[0x1b] 6690 1 T8 1 T10 2 T38 1
valid_sources[0x1c] 8427 1 T8 1 T10 1 T38 1
valid_sources[0x1d] 7712 1 T10 1 T61 1 T30 1
valid_sources[0x1e] 7667 1 T7 3 T10 1 T38 2
valid_sources[0x1f] 8560 1 T4 2 T10 2 T16 780
valid_sources[0x20] 7502 1 T8 1 T10 1 T38 3
valid_sources[0x21] 8172 1 T10 2 T16 768 T53 4
valid_sources[0x22] 7091 1 T8 1 T10 1 T16 853
valid_sources[0x23] 8072 1 T1 14 T4 1 T7 1
valid_sources[0x24] 7147 1 T4 1 T9 2 T16 823
valid_sources[0x25] 8683 1 T4 1 T7 1 T10 1
valid_sources[0x26] 7732 1 T1 1 T7 1 T9 1
valid_sources[0x27] 6956 1 T7 1 T9 1 T61 2
valid_sources[0x28] 7557 1 T9 1 T10 1 T16 824
valid_sources[0x29] 7268 1 T7 1 T10 3 T115 1
valid_sources[0x2a] 7922 1 T9 2 T10 3 T115 2
valid_sources[0x2b] 7449 1 T4 1 T7 1 T16 829
valid_sources[0x2c] 6899 1 T8 1 T10 2 T38 1
valid_sources[0x2d] 8512 1 T1 2 T4 1 T7 1
valid_sources[0x2e] 6921 1 T10 2 T38 1 T115 5
valid_sources[0x2f] 7171 1 T4 1 T8 1 T9 1
valid_sources[0x30] 6822 1 T7 1 T61 2 T38 3
valid_sources[0x31] 9138 1 T4 1 T7 3 T8 1
valid_sources[0x32] 6882 1 T8 1 T9 2 T115 1
valid_sources[0x33] 7064 1 T9 1 T61 7 T16 768
valid_sources[0x34] 7243 1 T4 2 T8 1 T9 3
valid_sources[0x35] 7532 1 T4 2 T8 1 T10 1
valid_sources[0x36] 6803 1 T10 1 T16 888 T17 172
valid_sources[0x37] 8300 1 T1 7 T7 2 T34 1
valid_sources[0x38] 7669 1 T34 1 T16 846 T17 199
valid_sources[0x39] 6991 1 T4 1 T8 2 T10 3
valid_sources[0x3a] 6879 1 T1 8 T12 1 T16 864
valid_sources[0x3b] 9181 1 T7 1 T9 1 T95 11
valid_sources[0x3c] 7326 1 T9 1 T10 1 T61 3
valid_sources[0x3d] 6827 1 T8 3 T10 1 T11 5
valid_sources[0x3e] 8620 1 T4 1 T10 1 T37 80
valid_sources[0x3f] 8080 1 T7 1 T61 3 T16 849
valid_sources[0x40] 7673 1 T7 1 T8 1 T10 2
valid_sources[0x41] 8757 1 T7 1 T9 1 T10 4
valid_sources[0x42] 7039 1 T34 4 T16 910 T53 3
valid_sources[0x43] 7189 1 T4 1 T8 3 T10 5
valid_sources[0x44] 7173 1 T8 3 T103 2 T46 1
valid_sources[0x45] 7959 1 T7 1 T103 3 T16 858
valid_sources[0x46] 7489 1 T7 3 T9 1 T38 2
valid_sources[0x47] 8061 1 T1 1 T4 2 T9 1
valid_sources[0x48] 8289 1 T8 2 T115 1 T16 785
valid_sources[0x49] 9086 1 T4 2 T7 3 T8 1
valid_sources[0x4a] 6827 1 T10 3 T13 4 T38 1
valid_sources[0x4b] 7148 1 T95 4 T16 804 T24 3
valid_sources[0x4c] 7642 1 T8 1 T61 3 T103 1
valid_sources[0x4d] 8388 1 T115 1 T16 797 T53 1
valid_sources[0x4e] 7755 1 T10 1 T16 847 T53 1
valid_sources[0x4f] 7380 1 T7 1 T8 1 T9 2
valid_sources[0x50] 7871 1 T9 3 T10 2 T61 1
valid_sources[0x51] 7024 1 T61 3 T103 3 T16 846
valid_sources[0x52] 7647 1 T7 1 T10 1 T16 801
valid_sources[0x53] 9183 1 T7 1 T16 831 T53 1
valid_sources[0x54] 7826 1 T9 1 T10 3 T115 1
valid_sources[0x55] 7331 1 T4 1 T7 1 T9 3
valid_sources[0x56] 7339 1 T10 2 T103 3 T16 809
valid_sources[0x57] 9669 1 T10 1 T34 1 T16 820
valid_sources[0x58] 6825 1 T7 1 T16 831 T53 1
valid_sources[0x59] 8063 1 T9 1 T38 1 T103 1
valid_sources[0x5a] 7189 1 T8 2 T9 1 T10 5
valid_sources[0x5b] 7980 1 T10 2 T16 839 T24 12
valid_sources[0x5c] 7108 1 T4 1 T7 1 T9 1
valid_sources[0x5d] 8233 1 T4 1 T8 3 T10 3
valid_sources[0x5e] 7892 1 T4 3 T10 3 T61 2
valid_sources[0x5f] 8707 1 T9 1 T16 817 T53 4
valid_sources[0x60] 7399 1 T95 8 T41 1 T16 879
valid_sources[0x61] 7360 1 T4 1 T10 1 T115 1
valid_sources[0x62] 7888 1 T7 1 T10 1 T16 819
valid_sources[0x63] 7786 1 T1 3 T8 1 T9 3
valid_sources[0x64] 6756 1 T1 3 T7 1 T9 1
valid_sources[0x65] 7272 1 T4 1 T7 1 T10 4
valid_sources[0x66] 7244 1 T7 1 T38 1 T16 816
valid_sources[0x67] 6944 1 T1 3 T4 1 T7 2
valid_sources[0x68] 7855 1 T4 1 T7 3 T8 1
valid_sources[0x69] 7753 1 T8 2 T10 1 T34 1
valid_sources[0x6a] 8226 1 T7 2 T9 1 T10 2
valid_sources[0x6b] 7835 1 T7 1 T8 2 T9 1
valid_sources[0x6c] 8187 1 T115 2 T16 826 T53 3
valid_sources[0x6d] 9226 1 T4 2 T7 3 T16 844
valid_sources[0x6e] 6697 1 T7 1 T9 1 T10 2
valid_sources[0x6f] 7347 1 T10 2 T95 5 T16 859
valid_sources[0x70] 7211 1 T4 1 T7 1 T12 2
valid_sources[0x71] 7957 1 T4 3 T9 1 T10 1
valid_sources[0x72] 8705 1 T4 1 T7 1 T9 2
valid_sources[0x73] 7563 1 T7 2 T10 3 T11 2
valid_sources[0x74] 7596 1 T7 1 T10 8 T16 817
valid_sources[0x75] 7463 1 T4 1 T7 1 T10 1
valid_sources[0x76] 7618 1 T8 1 T10 3 T34 2
valid_sources[0x77] 7084 1 T7 1 T9 1 T10 2
valid_sources[0x78] 6902 1 T7 1 T61 2 T16 783
valid_sources[0x79] 7675 1 T7 3 T10 2 T61 1
valid_sources[0x7a] 7410 1 T7 2 T10 1 T103 3
valid_sources[0x7b] 6714 1 T7 2 T10 2 T34 2
valid_sources[0x7c] 8092 1 T4 2 T38 2 T16 832
valid_sources[0x7d] 8214 1 T1 1 T8 1 T9 1
valid_sources[0x7e] 6562 1 T8 1 T10 1 T16 826
valid_sources[0x7f] 7791 1 T8 2 T9 1 T10 2
valid_sources[0x80] 7356 1 T4 2 T8 1 T10 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 469023 1 T1 10 T4 10 T7 9
values[0x0] all_enables biggest_size 699235 1 T16 76390 T17 19204 T18 18495
values[0x1] all_enables biggest_size 697410 1 T16 76496 T17 18993 T18 18565


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 138905 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1407861 1 T1 12 T2 4 T3 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 388255 1 T1 32 T5 23 T7 64
values[0x0] 536060 1 T2 6 T3 3 T6 3
values[0x1] 622451 1 T2 5 T3 7 T6 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 62399 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1484367 1 T1 20 T2 4 T3 2



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 6796 1 T16 670 T17 45 T18 372
valid_sources[0x01] 5701 1 T16 679 T17 251 T18 39
valid_sources[0x02] 5645 1 T42 1 T16 660 T17 137
valid_sources[0x03] 6384 1 T16 737 T24 3 T17 348
valid_sources[0x04] 5641 1 T13 1 T40 1 T64 1
valid_sources[0x05] 5976 1 T13 1 T61 1 T95 32
valid_sources[0x06] 6577 1 T16 675 T43 1 T56 2
valid_sources[0x07] 6608 1 T1 1 T16 683 T17 228
valid_sources[0x08] 5389 1 T1 2 T16 636 T17 38
valid_sources[0x09] 5758 1 T16 692 T17 5 T18 47
valid_sources[0x0a] 6186 1 T11 1 T61 1 T16 685
valid_sources[0x0b] 5680 1 T42 1 T16 628 T56 1
valid_sources[0x0c] 5742 1 T16 652 T17 76 T18 251
valid_sources[0x0d] 5343 1 T16 640 T17 180 T18 167
valid_sources[0x0e] 6174 1 T16 576 T56 2 T17 169
valid_sources[0x0f] 6539 1 T61 1 T16 634 T43 1
valid_sources[0x10] 7152 1 T41 3 T16 655 T17 280
valid_sources[0x11] 6734 1 T1 1 T2 1 T11 1
valid_sources[0x12] 6454 1 T61 1 T16 588 T17 136
valid_sources[0x13] 5985 1 T16 664 T17 259 T18 171
valid_sources[0x14] 5063 1 T16 686 T17 7 T116 1
valid_sources[0x15] 5393 1 T12 2 T61 1 T115 3
valid_sources[0x16] 5260 1 T16 687 T17 17 T18 113
valid_sources[0x17] 5687 1 T115 1 T16 571 T17 8
valid_sources[0x18] 5674 1 T11 1 T12 3 T115 1
valid_sources[0x19] 5690 1 T1 1 T115 1 T16 624
valid_sources[0x1a] 5619 1 T13 1 T115 1 T16 643
valid_sources[0x1b] 6874 1 T11 1 T16 732 T17 316
valid_sources[0x1c] 5963 1 T41 3 T16 641 T17 376
valid_sources[0x1d] 5378 1 T1 1 T12 1 T16 732
valid_sources[0x1e] 5946 1 T16 678 T17 113 T18 141
valid_sources[0x1f] 5939 1 T41 2 T16 699 T17 186
valid_sources[0x20] 7116 1 T16 681 T17 192 T18 531
valid_sources[0x21] 5451 1 T11 1 T12 1 T61 2
valid_sources[0x22] 6191 1 T11 1 T115 1 T16 691
valid_sources[0x23] 6195 1 T61 1 T115 2 T16 605
valid_sources[0x24] 6751 1 T46 2 T16 606 T17 667
valid_sources[0x25] 6499 1 T12 3 T30 1 T16 669
valid_sources[0x26] 6574 1 T115 1 T16 695 T17 193
valid_sources[0x27] 6448 1 T8 5 T16 645 T17 560
valid_sources[0x28] 5321 1 T64 2 T42 2 T16 671
valid_sources[0x29] 6701 1 T13 1 T46 2 T16 667
valid_sources[0x2a] 5538 1 T16 689 T17 9 T18 13
valid_sources[0x2b] 4803 1 T2 1 T115 1 T16 689
valid_sources[0x2c] 4623 1 T16 657 T17 60 T18 113
valid_sources[0x2d] 5575 1 T1 1 T42 1 T16 718
valid_sources[0x2e] 6208 1 T13 1 T42 1 T16 659
valid_sources[0x2f] 6275 1 T61 1 T46 2 T41 1
valid_sources[0x30] 6177 1 T11 1 T13 1 T61 1
valid_sources[0x31] 6273 1 T115 3 T16 626 T17 135
valid_sources[0x32] 5890 1 T61 1 T42 1 T16 598
valid_sources[0x33] 6230 1 T16 681 T17 113 T18 164
valid_sources[0x34] 5650 1 T12 2 T31 1 T30 1
valid_sources[0x35] 5952 1 T61 1 T16 680 T43 2
valid_sources[0x36] 6054 1 T11 1 T30 1 T16 642
valid_sources[0x37] 5916 1 T1 1 T61 1 T16 661
valid_sources[0x38] 5894 1 T2 1 T42 1 T16 607
valid_sources[0x39] 5946 1 T16 737 T17 167 T18 141
valid_sources[0x3a] 5595 1 T12 4 T16 683 T17 118
valid_sources[0x3b] 6058 1 T11 1 T13 1 T61 3
valid_sources[0x3c] 5757 1 T31 1 T41 1 T16 636
valid_sources[0x3d] 4836 1 T34 6 T16 583 T17 188
valid_sources[0x3e] 5592 1 T31 1 T34 4 T16 642
valid_sources[0x3f] 5756 1 T2 1 T13 3 T16 590
valid_sources[0x40] 6314 1 T13 2 T31 1 T16 626
valid_sources[0x41] 6804 1 T15 1 T16 549 T17 275
valid_sources[0x42] 5727 1 T42 2 T16 758 T17 130
valid_sources[0x43] 5449 1 T12 1 T61 2 T41 2
valid_sources[0x44] 6179 1 T61 1 T115 1 T16 729
valid_sources[0x45] 6171 1 T16 648 T24 1 T17 223
valid_sources[0x46] 6181 1 T1 1 T8 2 T63 1
valid_sources[0x47] 7368 1 T2 1 T11 1 T16 740
valid_sources[0x48] 6237 1 T16 646 T17 32 T18 122
valid_sources[0x49] 5285 1 T115 2 T16 693 T56 2
valid_sources[0x4a] 5436 1 T61 2 T16 654 T56 1
valid_sources[0x4b] 5650 1 T11 1 T42 2 T16 621
valid_sources[0x4c] 6909 1 T61 2 T29 1 T42 1
valid_sources[0x4d] 6202 1 T31 1 T16 584 T24 1
valid_sources[0x4e] 6254 1 T30 1 T16 642 T24 1
valid_sources[0x4f] 5342 1 T16 620 T17 14 T18 186
valid_sources[0x50] 5025 1 T31 1 T16 648 T17 29
valid_sources[0x51] 6239 1 T16 644 T17 271 T18 95
valid_sources[0x52] 6123 1 T46 1 T16 575 T17 9
valid_sources[0x53] 5251 1 T13 3 T16 633 T17 23
valid_sources[0x54] 5977 1 T1 1 T61 1 T16 647
valid_sources[0x55] 5957 1 T16 711 T43 1 T56 2
valid_sources[0x56] 5612 1 T30 1 T16 736 T17 9
valid_sources[0x57] 7785 1 T42 1 T16 758 T17 238
valid_sources[0x58] 6164 1 T16 609 T17 11 T18 287
valid_sources[0x59] 5685 1 T1 1 T16 665 T43 2
valid_sources[0x5a] 6405 1 T11 1 T117 1 T16 617
valid_sources[0x5b] 5730 1 T16 703 T24 2 T17 59
valid_sources[0x5c] 5832 1 T1 1 T42 1 T16 792
valid_sources[0x5d] 6167 1 T11 1 T41 1 T16 603
valid_sources[0x5e] 6664 1 T8 1 T11 1 T16 699
valid_sources[0x5f] 6350 1 T61 2 T16 625 T17 80
valid_sources[0x60] 6081 1 T11 1 T42 1 T16 658
valid_sources[0x61] 6841 1 T1 1 T8 4 T16 656
valid_sources[0x62] 5895 1 T1 1 T30 1 T115 2
valid_sources[0x63] 5372 1 T61 1 T16 656 T43 1
valid_sources[0x64] 6672 1 T8 2 T16 771 T43 1
valid_sources[0x65] 5948 1 T61 1 T16 762 T17 279
valid_sources[0x66] 5526 1 T27 1 T16 616 T17 131
valid_sources[0x67] 6303 1 T8 2 T46 9 T16 623
valid_sources[0x68] 6650 1 T61 1 T16 726 T56 1
valid_sources[0x69] 5950 1 T16 629 T17 174 T18 227
valid_sources[0x6a] 5043 1 T14 28 T61 1 T115 1
valid_sources[0x6b] 5346 1 T2 1 T11 1 T42 1
valid_sources[0x6c] 5417 1 T31 1 T22 1 T16 624
valid_sources[0x6d] 5357 1 T13 1 T16 672 T17 62
valid_sources[0x6e] 6347 1 T13 1 T42 1 T16 674
valid_sources[0x6f] 6058 1 T16 691 T24 1 T17 32
valid_sources[0x70] 5795 1 T16 648 T17 184 T18 421
valid_sources[0x71] 5755 1 T16 661 T56 1 T17 9
valid_sources[0x72] 5612 1 T30 1 T16 634 T17 112
valid_sources[0x73] 6707 1 T61 1 T16 660 T43 1
valid_sources[0x74] 6232 1 T31 1 T16 656 T56 1
valid_sources[0x75] 7101 1 T12 2 T16 609 T17 381
valid_sources[0x76] 5847 1 T16 604 T17 150 T18 352
valid_sources[0x77] 6534 1 T16 641 T17 106 T18 183
valid_sources[0x78] 6286 1 T16 696 T56 1 T17 373
valid_sources[0x79] 5005 1 T13 1 T61 1 T41 1
valid_sources[0x7a] 5319 1 T115 2 T16 624 T24 1
valid_sources[0x7b] 5405 1 T11 1 T16 670 T24 1
valid_sources[0x7c] 5712 1 T13 1 T61 1 T16 687
valid_sources[0x7d] 6185 1 T11 1 T31 2 T34 2
valid_sources[0x7e] 6628 1 T30 3 T16 642 T43 1
valid_sources[0x7f] 5767 1 T16 656 T43 1 T24 1
valid_sources[0x80] 5959 1 T30 1 T64 1 T16 722



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 357041 1 T1 12 T5 14 T7 28
values[0x0] all_enables biggest_size 525125 1 T2 2 T6 2 T16 57257
values[0x1] all_enables biggest_size 525695 1 T2 2 T3 1 T6 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%