Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3373709

1

T1

55

T4

88

T7

144

full_word

2173045

1

T1

10

T4

10

T7

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5546454	1			T1	65		T4	98		T7	153
auto[TlIntgErrCmd]	93	1			T58	6		T59	8		T60	6
auto[TlIntgErrData]	97	1			T58	5		T59	5		T60	6
auto[TlIntgErrBoth]	110	1			T58	9		T59	7		T60	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

881383

1

T1

65

T4

98

T7

153

auto[1]

4665371

1

T16

516025

T17

133123

T18

126228

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	367756	1			T1	55		T4	88		T7	144
auto[TlIntgErrNone]	partial	auto[1]	3005678	1			T16	334096		T17	87430		T18	82017
auto[TlIntgErrNone]	full_word	auto[0]	513493	1			T1	10		T4	10		T7	9
auto[TlIntgErrNone]	full_word	auto[1]	1659527	1			T16	181929		T17	45693		T18	44211
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T58	1		T59	3		T60	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T58	4		T59	4		T60	3
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T58	1		T59	1		T105	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T58	3		T59	1		T60	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T58	2		T59	4		T60	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T106	1		T107	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T106	1		T109	1		T105	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T58	6		T59	1		T60	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T58	3		T59	6		T60	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T108	1		T110	1		T111	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T60	1		T108	1		T112	1