Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.38	96.97	93.02	97.88	100.00	98.37	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.23	91.60	85.20	99.07		95.29	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
212	1	1
258	1	1
313	1	1
414	8	8
415	8	8
417	8	8
418	8	8
420	8	8
421	8	8
425	1	1
427	1	1
430	1	1
431	1	1
432	1	1
433	1	1
438	1	1
442	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       212
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       258
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T13,T14
1	1	Covered	T1,T4,T7

 LINE       418
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T32,T33
1	0	Not Covered

 LINE       427
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T30
1	0	Covered	T5,T15,T13

 LINE       438
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       442
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T13,T14,T30
0	1	0	Covered	T5,T15,T13
1	0	0	Covered	T31,T32,T33

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T4,T7	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T9,T13,T14	Yes	T3,T15,T13	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T4,T7	Yes	T1,T3,T4	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T4,T7	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T4,T7	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T4,T7	Yes	T1,T3,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T4,T7	Yes	T1,T3,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T3,T15,T13	Yes	T9,T15,T13	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T11,T34	Yes	T3,T11,T27	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T5,T7	Yes	T1,T5,T7	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T5,*T7	Yes	T1,T5,T7	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T5,T7	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T1,T5,T7	Yes	T1,T2,T3	OUTPUT
kmac_data_i.error	No	Yes	T15,T27,T22	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T5,T15,T13	Yes	T1,T5,T7	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T5,T7	Yes	T8,T13,T14	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	212	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	186217347	186036311	0	0
BusRomIndicesMatch_A	186206800	186031399	0	0
FpvSecCmFifoRptrCheck_A	186217347	0	0	0
FpvSecCmFifoWptrCheck_A	186217347	0	0	0
FpvSecCmRegWeOnehotCheck_A	186217347	90	0	0
KeymgrDataODataKnown_A	186217347	71993367	0	0
KeymgrDataODataKnown_AKnownEnable	186217347	186036311	0	0
KeymgrDataOValidKnown_A	186217347	186036311	0	0
KeymgrValidChk_A	186217347	0	0	322
KmacDataODataKnown_A	186217347	113912149	0	0
KmacDataODataKnown_AKnownEnable	186217347	186036311	0	0
KmacDataOValidKnown_A	186217347	186036311	0	0
PwrmgrDataChk_A	186217347	0	0	322
PwrmgrDataOKnown_A	186217347	186036311	0	0
RegsTlOAReadyKnown_A	186217347	186036311	0	0
RegsTlODDataKnown_A	186217347	10987300	0	0
RegsTlODDataKnown_AKnownEnable	186217347	186036311	0	0
RegsTlODValidKnown_A	186217347	186036311	0	0
RomTlOAReadyKnown_A	186217347	186036311	0	0
RomTlODDataKnown_A	186217347	16408276	0	0
RomTlODDataKnown_AKnownEnable	186217347	186036311	0	0
RomTlODValidKnown_A	186217347	186036311	0	0
StabilityChkKmac_A	186217347	113909647	0	0
StabilityChkkeymgr_A	186217347	71992165	0	0
TlAccessChk_A	186217347	114042944	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	186217347	90	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	186217347	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	186217347	538	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	186217347	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186206800	186031399	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	90	0	0
T22	16846	0	0	0
T28	363038	0	0	0
T29	33060	0	0	0
T30	165588	0	0	0
T31	57098	20	0	0
T32	0	20	0	0
T33	0	20	0	0
T34	394217	0	0	0
T35	0	10	0	0
T36	0	20	0	0
T37	91900	0	0	0
T38	17905	0	0	0
T39	278699	0	0	0
T40	212093	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	71993367	0	0
T1	413196	1221	0	0
T2	8541	279	0	0
T3	8547	269	0	0
T4	152987	887	0	0
T5	162014	9518	0	0
T6	119908	64	0	0
T7	506757	3388	0	0
T8	247267	1764	0	0
T9	166541	931	0	0
T10	206290	1240	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	0	0	322

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	113912149	0	0
T1	413196	411581	0	0
T2	8541	8184	0	0
T3	8547	8184	0	0
T4	152987	151973	0	0
T5	162014	160729	0	0
T6	119908	119722	0	0
T7	506757	502777	0	0
T8	247267	245188	0	0
T9	166541	165495	0	0
T10	206290	204897	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	0	0	322

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	10987300	0	0
T1	413196	32	0	0
T2	8541	11	0	0
T3	8547	10	0	0
T4	152987	0	0	0
T5	162014	92	0	0
T6	119908	41	0	0
T7	506757	64	0	0
T8	247267	160	0	0
T9	166541	0	0	0
T10	206290	0	0	0
T11	0	103	0	0
T13	0	167	0	0
T15	0	1	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	16408276	0	0
T1	413196	65	0	0
T2	8541	0	0	0
T3	8547	0	0	0
T4	152987	98	0	0
T5	162014	0	0	0
T6	119908	0	0	0
T7	506757	845	0	0
T8	247267	91	0	0
T9	166541	92	0	0
T10	206290	319	0	0
T11	0	379	0	0
T12	0	341	0	0
T13	0	6	0	0
T14	0	3	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	186036311	0	0
T1	413196	413011	0	0
T2	8541	8484	0	0
T3	8547	8474	0	0
T4	152987	152933	0	0
T5	162014	161794	0	0
T6	119908	119824	0	0
T7	506757	506451	0	0
T8	247267	247159	0	0
T9	166541	166460	0	0
T10	206290	206240	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	113909647	0	0
T1	413196	411579	0	0
T2	8541	8183	0	0
T3	8547	8183	0	0
T4	152987	151972	0	0
T5	162014	160726	0	0
T6	119908	119721	0	0
T7	506757	502773	0	0
T8	247267	245186	0	0
T9	166541	165494	0	0
T10	206290	204896	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	71992165	0	0
T1	413196	1219	0	0
T2	8541	278	0	0
T3	8547	268	0	0
T4	152987	886	0	0
T5	162014	9512	0	0
T6	119908	63	0	0
T7	506757	3385	0	0
T8	247267	1762	0	0
T9	166541	930	0	0
T10	206290	1239	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	114042944	0	0
T1	413196	411790	0	0
T2	8541	8205	0	0
T3	8547	8205	0	0
T4	152987	152046	0	0
T5	162014	160842	0	0
T6	119908	119760	0	0
T7	506757	503063	0	0
T8	247267	245395	0	0
T9	166541	165529	0	0
T10	206290	205000	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	90	0	0
T22	16846	0	0	0
T28	363038	0	0	0
T29	33060	0	0	0
T30	165588	0	0	0
T31	57098	20	0	0
T32	0	20	0	0
T33	0	20	0	0
T34	394217	0	0	0
T35	0	10	0	0
T36	0	20	0	0
T37	91900	0	0	0
T38	17905	0	0	0
T39	278699	0	0	0
T40	212093	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	538	0	0
T5	162014	5	0	0
T6	119908	0	0	0
T7	506757	0	0	0
T8	247267	0	0	0
T9	166541	0	0	0
T10	206290	0	0	0
T11	385477	0	0	0
T13	269560	15	0	0
T14	0	16	0	0
T15	244596	0	0	0
T27	416944	0	0	0
T30	0	5	0	0
T31	0	20	0	0
T41	0	15	0	0
T42	0	15	0	0
T43	0	25	0	0
T44	0	6	0	0
T45	0	10	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186217347	0	0	0