Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72656	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1761920

1

T1

30961

T2

6

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	478213	1			T1	8491		T2	6		T3	74
values[0x0]	666643	1			T1	11651		T6	10575		T11	17716
values[0x1]	689720	1			T1	12070		T6	10913		T11	18034

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1796813

1

T1

31521

T2

6

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7251	1			T1	115		T6	93		T60	44
valid_sources[0x01]	6982	1			T1	113		T6	126		T8	1
valid_sources[0x02]	7934	1			T1	136		T6	142		T10	1
valid_sources[0x03]	6759	1			T1	159		T4	1		T6	82
valid_sources[0x04]	7338	1			T1	169		T6	65		T105	1
valid_sources[0x05]	6807	1			T1	112		T2	4		T6	53
valid_sources[0x06]	7463	1			T1	150		T4	4		T6	86
valid_sources[0x07]	6717	1			T1	131		T6	122		T14	3
valid_sources[0x08]	7036	1			T1	142		T4	1		T6	96
valid_sources[0x09]	6646	1			T1	86		T6	119		T14	3
valid_sources[0x0a]	7780	1			T1	136		T4	2		T6	138
valid_sources[0x0b]	6706	1			T1	94		T6	68		T8	1
valid_sources[0x0c]	7327	1			T1	99		T6	104		T10	2
valid_sources[0x0d]	6957	1			T1	118		T6	109		T10	1
valid_sources[0x0e]	7077	1			T1	117		T6	109		T8	2
valid_sources[0x0f]	6968	1			T1	142		T4	3		T6	105
valid_sources[0x10]	6723	1			T1	128		T4	5		T6	80
valid_sources[0x11]	7006	1			T1	198		T6	169		T14	4
valid_sources[0x12]	6958	1			T1	154		T4	2		T6	114
valid_sources[0x13]	6797	1			T1	108		T6	104		T10	2
valid_sources[0x14]	7275	1			T1	91		T4	1		T6	114
valid_sources[0x15]	7146	1			T1	110		T6	119		T10	3
valid_sources[0x16]	7046	1			T1	101		T6	116		T10	6
valid_sources[0x17]	7396	1			T1	79		T6	126		T10	3
valid_sources[0x18]	7290	1			T1	122		T6	90		T8	1
valid_sources[0x19]	7426	1			T1	73		T3	7		T4	1
valid_sources[0x1a]	6738	1			T1	125		T6	95		T8	1
valid_sources[0x1b]	8144	1			T1	172		T6	83		T11	179
valid_sources[0x1c]	7306	1			T1	125		T6	147		T10	3
valid_sources[0x1d]	6850	1			T1	173		T4	1		T6	138
valid_sources[0x1e]	6761	1			T1	98		T4	1		T6	81
valid_sources[0x1f]	6871	1			T1	121		T6	100		T14	2
valid_sources[0x20]	6754	1			T1	82		T4	2		T6	97
valid_sources[0x21]	7135	1			T1	160		T6	116		T8	2
valid_sources[0x22]	7949	1			T1	140		T6	186		T10	1
valid_sources[0x23]	7795	1			T1	160		T6	109		T14	1
valid_sources[0x24]	7353	1			T1	120		T6	183		T10	3
valid_sources[0x25]	6585	1			T1	125		T6	116		T10	2
valid_sources[0x26]	7139	1			T1	128		T6	113		T10	3
valid_sources[0x27]	7219	1			T1	125		T4	2		T6	131
valid_sources[0x28]	7063	1			T1	144		T6	93		T8	2
valid_sources[0x29]	6771	1			T1	90		T6	94		T10	2
valid_sources[0x2a]	7086	1			T1	115		T4	1		T6	119
valid_sources[0x2b]	6916	1			T1	156		T6	148		T10	1
valid_sources[0x2c]	7087	1			T1	112		T4	1		T6	148
valid_sources[0x2d]	7209	1			T1	99		T3	3		T6	82
valid_sources[0x2e]	6800	1			T1	111		T6	82		T10	1
valid_sources[0x2f]	7726	1			T1	88		T6	99		T8	1
valid_sources[0x30]	7146	1			T1	123		T6	122		T10	4
valid_sources[0x31]	6903	1			T1	150		T4	3		T6	113
valid_sources[0x32]	7237	1			T1	189		T6	111		T10	2
valid_sources[0x33]	7066	1			T1	127		T6	108		T8	1
valid_sources[0x34]	9853	1			T1	191		T6	195		T8	1
valid_sources[0x35]	8243	1			T1	103		T6	136		T10	3
valid_sources[0x36]	6783	1			T1	152		T6	131		T8	1
valid_sources[0x37]	6827	1			T1	98		T4	2		T6	128
valid_sources[0x38]	7399	1			T1	116		T4	1		T6	90
valid_sources[0x39]	7154	1			T1	120		T6	100		T10	3
valid_sources[0x3a]	8335	1			T1	118		T4	1		T6	134
valid_sources[0x3b]	7104	1			T1	110		T6	143		T10	1
valid_sources[0x3c]	6878	1			T1	140		T4	1		T6	129
valid_sources[0x3d]	6659	1			T1	161		T6	86		T10	1
valid_sources[0x3e]	8208	1			T1	123		T4	1		T6	91
valid_sources[0x3f]	7123	1			T1	172		T6	108		T10	1
valid_sources[0x40]	6705	1			T1	158		T4	1		T6	121
valid_sources[0x41]	7129	1			T1	180		T4	3		T6	76
valid_sources[0x42]	6663	1			T1	115		T4	1		T6	72
valid_sources[0x43]	7091	1			T1	120		T6	76		T8	1
valid_sources[0x44]	7316	1			T1	86		T6	60		T11	192
valid_sources[0x45]	7297	1			T1	112		T4	1		T6	91
valid_sources[0x46]	7205	1			T1	140		T6	107		T10	4
valid_sources[0x47]	6831	1			T1	159		T4	1		T6	135
valid_sources[0x48]	7216	1			T1	96		T4	1		T6	125
valid_sources[0x49]	6834	1			T1	144		T4	3		T6	133
valid_sources[0x4a]	7226	1			T1	143		T6	136		T10	3
valid_sources[0x4b]	6837	1			T1	115		T6	153		T7	13
valid_sources[0x4c]	7292	1			T1	131		T2	1		T4	2
valid_sources[0x4d]	6708	1			T1	129		T6	136		T14	4
valid_sources[0x4e]	7090	1			T1	129		T6	125		T10	2
valid_sources[0x4f]	7510	1			T1	100		T6	109		T10	2
valid_sources[0x50]	6845	1			T1	120		T6	78		T10	2
valid_sources[0x51]	7286	1			T1	151		T3	2		T6	116
valid_sources[0x52]	6677	1			T1	148		T6	105		T8	1
valid_sources[0x53]	7039	1			T1	188		T6	147		T10	1
valid_sources[0x54]	8257	1			T1	137		T6	109		T8	1
valid_sources[0x55]	6942	1			T1	150		T6	166		T10	2
valid_sources[0x56]	7256	1			T1	81		T6	90		T10	3
valid_sources[0x57]	6762	1			T1	127		T4	2		T6	103
valid_sources[0x58]	7251	1			T1	144		T6	80		T8	1
valid_sources[0x59]	7448	1			T1	121		T4	1		T6	98
valid_sources[0x5a]	6613	1			T1	166		T6	94		T10	1
valid_sources[0x5b]	7126	1			T1	138		T6	105		T10	4
valid_sources[0x5c]	6794	1			T1	173		T4	3		T6	134
valid_sources[0x5d]	7610	1			T1	146		T3	6		T6	103
valid_sources[0x5e]	6520	1			T1	149		T6	86		T10	3
valid_sources[0x5f]	7115	1			T1	120		T4	2		T6	105
valid_sources[0x60]	6720	1			T1	134		T4	6		T6	113
valid_sources[0x61]	6826	1			T1	134		T6	105		T10	2
valid_sources[0x62]	6596	1			T1	133		T6	123		T10	5
valid_sources[0x63]	7501	1			T1	116		T4	1		T6	165
valid_sources[0x64]	7176	1			T1	120		T6	123		T8	2
valid_sources[0x65]	7126	1			T1	112		T6	109		T10	1
valid_sources[0x66]	7152	1			T1	151		T6	101		T10	1
valid_sources[0x67]	6876	1			T1	125		T6	126		T8	1
valid_sources[0x68]	6613	1			T1	112		T4	1		T6	101
valid_sources[0x69]	6974	1			T1	114		T4	1		T6	143
valid_sources[0x6a]	7039	1			T1	164		T6	102		T10	2
valid_sources[0x6b]	7708	1			T1	94		T6	118		T10	3
valid_sources[0x6c]	7118	1			T1	160		T4	2		T5	1
valid_sources[0x6d]	7301	1			T1	115		T6	100		T14	6
valid_sources[0x6e]	6469	1			T1	93		T6	84		T10	2
valid_sources[0x6f]	6980	1			T1	147		T6	106		T10	1
valid_sources[0x70]	7120	1			T1	115		T6	113		T10	2
valid_sources[0x71]	7125	1			T1	117		T6	112		T8	1
valid_sources[0x72]	7053	1			T1	129		T3	6		T6	81
valid_sources[0x73]	6938	1			T1	138		T6	137		T14	4
valid_sources[0x74]	7488	1			T1	144		T4	2		T5	1
valid_sources[0x75]	7193	1			T1	89		T6	121		T10	2
valid_sources[0x76]	7399	1			T1	135		T4	4		T6	148
valid_sources[0x77]	7301	1			T1	113		T4	2		T6	98
valid_sources[0x78]	7353	1			T1	84		T6	91		T10	2
valid_sources[0x79]	6606	1			T1	118		T4	1		T6	142
valid_sources[0x7a]	6976	1			T1	94		T3	3		T6	89
valid_sources[0x7b]	7735	1			T1	87		T6	100		T10	2
valid_sources[0x7c]	7455	1			T1	134		T3	4		T4	2
valid_sources[0x7d]	6912	1			T1	136		T6	97		T11	185
valid_sources[0x7e]	7439	1			T1	180		T6	98		T10	1
valid_sources[0x7f]	6941	1			T1	135		T6	99		T10	1
valid_sources[0x80]	6870	1			T1	144		T4	1		T6	118

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

442426

1

T1

7879

T2

6

T3

9

values[0x0]

all_enables

biggest_size

660654

1

T1

11550

T6

10492

T11

17568

values[0x1]

all_enables

biggest_size

658840

1

T1

11532

T6

10437

T11

17323

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	132969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1349566

1

T1

23306

T2

15

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	370309	1			T1	6516		T2	32		T3	32
values[0x0]	514599	1			T1	8754		T6	6865		T19	2
values[0x1]	597627	1			T1	10307		T6	8320		T19	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59689	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1422846

1

T1

24584

T2

18

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6176	1			T1	277		T6	151		T11	124
valid_sources[0x01]	5686	1			T1	29		T6	8		T103	1
valid_sources[0x02]	6102	1			T1	397		T6	28		T11	114
valid_sources[0x03]	5875	1			T1	9		T6	8		T11	178
valid_sources[0x04]	6370	1			T1	123		T3	1		T6	83
valid_sources[0x05]	6371	1			T1	5		T6	87		T35	1
valid_sources[0x06]	5376	1			T1	15		T6	56		T35	2
valid_sources[0x07]	5523	1			T1	29		T6	4		T70	2
valid_sources[0x08]	5870	1			T1	189		T6	5		T103	1
valid_sources[0x09]	5476	1			T1	169		T6	9		T122	1
valid_sources[0x0a]	6275	1			T1	119		T6	73		T103	1
valid_sources[0x0b]	5290	1			T1	23		T6	7		T11	161
valid_sources[0x0c]	5437	1			T1	97		T6	197		T15	1
valid_sources[0x0d]	6054	1			T1	15		T6	12		T11	172
valid_sources[0x0e]	5859	1			T1	14		T6	210		T103	3
valid_sources[0x0f]	5099	1			T1	4		T6	7		T35	1
valid_sources[0x10]	5272	1			T1	4		T6	6		T103	1
valid_sources[0x11]	5904	1			T1	233		T6	58		T11	143
valid_sources[0x12]	5776	1			T1	96		T6	318		T11	108
valid_sources[0x13]	6383	1			T1	8		T6	4		T46	1
valid_sources[0x14]	6469	1			T1	120		T6	14		T11	170
valid_sources[0x15]	6115	1			T1	219		T6	141		T103	2
valid_sources[0x16]	5903	1			T1	136		T3	1		T6	125
valid_sources[0x17]	5427	1			T1	293		T6	205		T11	154
valid_sources[0x18]	5780	1			T1	8		T6	3		T11	100
valid_sources[0x19]	6456	1			T1	161		T6	99		T15	4
valid_sources[0x1a]	5621	1			T1	5		T6	8		T10	160
valid_sources[0x1b]	5697	1			T1	34		T6	160		T122	2
valid_sources[0x1c]	5844	1			T1	270		T6	11		T69	1
valid_sources[0x1d]	5558	1			T1	16		T3	1		T6	34
valid_sources[0x1e]	6262	1			T1	25		T3	1		T6	147
valid_sources[0x1f]	5552	1			T1	7		T6	7		T11	186
valid_sources[0x20]	5274	1			T1	15		T6	7		T13	1
valid_sources[0x21]	4982	1			T1	3		T6	114		T11	106
valid_sources[0x22]	5722	1			T1	5		T6	12		T103	1
valid_sources[0x23]	5426	1			T1	40		T6	66		T103	1
valid_sources[0x24]	6068	1			T1	5		T6	33		T69	1
valid_sources[0x25]	5544	1			T1	89		T6	70		T72	1
valid_sources[0x26]	6264	1			T1	20		T6	94		T103	1
valid_sources[0x27]	5627	1			T1	138		T6	136		T11	172
valid_sources[0x28]	5299	1			T1	69		T5	1		T6	6
valid_sources[0x29]	6217	1			T1	2		T6	124		T103	1
valid_sources[0x2a]	6077	1			T1	158		T6	150		T103	1
valid_sources[0x2b]	5680	1			T1	53		T5	1		T6	86
valid_sources[0x2c]	5749	1			T1	130		T6	13		T103	2
valid_sources[0x2d]	5455	1			T1	10		T6	319		T69	1
valid_sources[0x2e]	6379	1			T1	610		T6	10		T103	1
valid_sources[0x2f]	6026	1			T1	19		T6	5		T15	4
valid_sources[0x30]	5140	1			T1	14		T6	148		T11	108
valid_sources[0x31]	6763	1			T1	249		T6	255		T11	156
valid_sources[0x32]	5155	1			T1	11		T6	173		T122	1
valid_sources[0x33]	5820	1			T1	103		T5	1		T6	3
valid_sources[0x34]	5590	1			T1	348		T3	1		T6	48
valid_sources[0x35]	5102	1			T1	93		T6	9		T122	1
valid_sources[0x36]	5643	1			T1	199		T6	11		T103	1
valid_sources[0x37]	5276	1			T1	3		T6	10		T11	115
valid_sources[0x38]	5080	1			T1	276		T6	178		T11	120
valid_sources[0x39]	5978	1			T1	15		T6	13		T11	130
valid_sources[0x3a]	5022	1			T1	17		T6	54		T103	2
valid_sources[0x3b]	5834	1			T1	20		T6	644		T35	2
valid_sources[0x3c]	5494	1			T1	3		T6	2		T45	1
valid_sources[0x3d]	5818	1			T1	277		T6	112		T11	115
valid_sources[0x3e]	5810	1			T1	223		T6	4		T103	2
valid_sources[0x3f]	5927	1			T1	409		T3	3		T6	148
valid_sources[0x40]	6077	1			T1	210		T6	94		T11	175
valid_sources[0x41]	6236	1			T1	21		T6	273		T11	140
valid_sources[0x42]	5883	1			T1	332		T6	17		T103	1
valid_sources[0x43]	5912	1			T1	14		T6	130		T11	175
valid_sources[0x44]	5341	1			T1	12		T6	26		T70	3
valid_sources[0x45]	5378	1			T1	70		T6	4		T69	1
valid_sources[0x46]	5825	1			T1	8		T6	13		T46	1
valid_sources[0x47]	7048	1			T1	15		T6	187		T122	7
valid_sources[0x48]	5288	1			T1	109		T6	86		T11	134
valid_sources[0x49]	5730	1			T1	10		T5	1		T6	45
valid_sources[0x4a]	4941	1			T1	18		T6	2		T11	143
valid_sources[0x4b]	5733	1			T1	139		T6	19		T46	1
valid_sources[0x4c]	5282	1			T1	147		T6	103		T69	2
valid_sources[0x4d]	6566	1			T1	382		T3	1		T6	33
valid_sources[0x4e]	5918	1			T1	20		T6	3		T103	1
valid_sources[0x4f]	5095	1			T1	4		T6	142		T123	1
valid_sources[0x50]	5723	1			T1	5		T6	4		T103	2
valid_sources[0x51]	5204	1			T1	25		T3	1		T103	1
valid_sources[0x52]	5254	1			T1	351		T5	1		T6	4
valid_sources[0x53]	5695	1			T1	322		T6	160		T103	1
valid_sources[0x54]	6266	1			T1	11		T6	8		T11	163
valid_sources[0x55]	5374	1			T1	107		T6	22		T103	1
valid_sources[0x56]	6230	1			T1	204		T3	1		T6	102
valid_sources[0x57]	5766	1			T1	26		T6	24		T11	153
valid_sources[0x58]	5741	1			T1	136		T6	72		T11	132
valid_sources[0x59]	6051	1			T1	221		T6	244		T103	3
valid_sources[0x5a]	6000	1			T1	6		T6	16		T72	1
valid_sources[0x5b]	5313	1			T1	56		T6	44		T72	1
valid_sources[0x5c]	5840	1			T1	10		T6	7		T103	2
valid_sources[0x5d]	5349	1			T1	8		T6	1		T103	1
valid_sources[0x5e]	5719	1			T1	83		T6	27		T103	1
valid_sources[0x5f]	6162	1			T1	8		T6	28		T69	1
valid_sources[0x60]	5286	1			T1	31		T3	1		T6	3
valid_sources[0x61]	5904	1			T1	268		T2	32		T6	240
valid_sources[0x62]	6056	1			T1	5		T6	145		T11	160
valid_sources[0x63]	5963	1			T1	140		T3	1		T6	2
valid_sources[0x64]	5860	1			T1	19		T6	7		T69	1
valid_sources[0x65]	5465	1			T1	112		T3	1		T6	40
valid_sources[0x66]	5760	1			T1	131		T6	8		T11	154
valid_sources[0x67]	5478	1			T1	125		T6	19		T103	1
valid_sources[0x68]	5081	1			T1	11		T5	1		T6	6
valid_sources[0x69]	6175	1			T1	10		T6	11		T71	25
valid_sources[0x6a]	5573	1			T1	88		T6	2		T11	161
valid_sources[0x6b]	5969	1			T1	21		T6	179		T103	1
valid_sources[0x6c]	5922	1			T1	29		T3	1		T5	1
valid_sources[0x6d]	5808	1			T1	4		T6	128		T103	2
valid_sources[0x6e]	5898	1			T1	278		T6	11		T72	1
valid_sources[0x6f]	5628	1			T1	4		T6	5		T11	147
valid_sources[0x70]	5792	1			T1	9		T6	297		T69	1
valid_sources[0x71]	5602	1			T1	96		T6	178		T22	7
valid_sources[0x72]	6161	1			T1	4		T6	113		T103	1
valid_sources[0x73]	6512	1			T1	112		T6	180		T11	139
valid_sources[0x74]	5555	1			T1	20		T6	83		T11	115
valid_sources[0x75]	5740	1			T1	184		T6	3		T11	186
valid_sources[0x76]	5509	1			T1	1		T6	6		T72	1
valid_sources[0x77]	5618	1			T1	131		T6	17		T122	1
valid_sources[0x78]	5958	1			T1	16		T6	82		T11	157
valid_sources[0x79]	5123	1			T1	8		T6	7		T103	1
valid_sources[0x7a]	5825	1			T1	2		T6	13		T35	3
valid_sources[0x7b]	6212	1			T1	243		T6	2		T11	164
valid_sources[0x7c]	5250	1			T1	131		T6	195		T103	1
valid_sources[0x7d]	5409	1			T1	12		T6	12		T103	1
valid_sources[0x7e]	5585	1			T1	226		T6	15		T72	1
valid_sources[0x7f]	5445	1			T1	16		T5	1		T6	31
valid_sources[0x80]	5438	1			T1	29		T6	3		T69	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

341455

1

T1

5988

T2

15

T3

11

values[0x0]

all_enables

biggest_size

503795

1

T1

8605

T6

6715

T19

1

values[0x1]

all_enables

biggest_size

504316

1

T1

8713

T6

6909

T19

3