Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3262537

1

T1

59116

T3

65

T4

141

full_word

2059496

1

T1

36399

T2

4

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5321733	1			T1	95515		T2	4		T3	74
auto[TlIntgErrCmd]	108	1			T52	7		T53	11		T54	7
auto[TlIntgErrData]	81	1			T52	1		T53	4		T54	5
auto[TlIntgErrBoth]	111	1			T52	2		T53	5		T54	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

834614

1

T1

15008

T2

4

T3

74

auto[1]

4487419

1

T1

80507

T6

67865

T11

111815

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	349527	1			T1	6378		T3	65		T4	141
auto[TlIntgErrNone]	partial	auto[1]	2912742	1			T1	52738		T6	43076		T11	70745
auto[TlIntgErrNone]	full_word	auto[0]	484947	1			T1	8630		T2	4		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	1574517	1			T1	27769		T6	24789		T11	41070
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T52	1		T53	4		T54	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T52	4		T53	7		T54	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T52	1		T54	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T52	1		T117	1		T118	2
auto[TlIntgErrData]	partial	auto[0]	30	1			T53	1		T54	3		T110	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T52	1		T53	2		T110	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T111	1		T119	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T53	1		T54	2		T108	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T53	2		T54	5		T110	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T52	2		T53	3		T54	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T111	1		T108	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T111	1		T113	1		T120	1