Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	69477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1441315

1

T2

40

T3

3

T4

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	403382	1			T2	353		T3	3		T4	151
values[0x0]	542580	1			T11	13168		T12	25405		T13	17345
values[0x1]	564830	1			T11	13928		T12	26438		T13	18398

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1475564

1

T2

217

T3

3

T4

93

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5338	1			T4	1		T5	2		T7	1
valid_sources[0x01]	6456	1			T2	1		T4	1		T20	2
valid_sources[0x02]	5906	1			T2	9		T4	3		T5	2
valid_sources[0x03]	5514	1			T2	1		T5	2		T31	1
valid_sources[0x04]	5387	1			T5	1		T9	1		T19	2
valid_sources[0x05]	5792	1			T2	5		T5	2		T20	1
valid_sources[0x06]	5408	1			T2	6		T9	1		T20	1
valid_sources[0x07]	6273	1			T2	2		T5	1		T9	1
valid_sources[0x08]	5468	1			T2	5		T5	2		T9	1
valid_sources[0x09]	5665	1			T2	1		T4	1		T5	1
valid_sources[0x0a]	5415	1			T2	4		T20	1		T18	2
valid_sources[0x0b]	6199	1			T4	1		T101	7		T11	123
valid_sources[0x0c]	6862	1			T20	3		T105	1		T11	145
valid_sources[0x0d]	5879	1			T3	1		T19	1		T101	6
valid_sources[0x0e]	6490	1			T2	1		T4	2		T9	1
valid_sources[0x0f]	5687	1			T5	1		T7	2		T9	3
valid_sources[0x10]	6465	1			T5	1		T9	2		T20	1
valid_sources[0x11]	6031	1			T2	2		T4	1		T5	1
valid_sources[0x12]	7030	1			T2	6		T5	3		T9	2
valid_sources[0x13]	5384	1			T2	2		T7	1		T105	1
valid_sources[0x14]	5368	1			T2	2		T4	1		T5	2
valid_sources[0x15]	6053	1			T2	4		T9	2		T20	1
valid_sources[0x16]	6269	1			T2	1		T4	2		T9	1
valid_sources[0x17]	6014	1			T2	1		T7	1		T17	1
valid_sources[0x18]	5082	1			T5	1		T20	3		T101	5
valid_sources[0x19]	5375	1			T2	5		T4	1		T5	1
valid_sources[0x1a]	5408	1			T2	3		T4	1		T5	2
valid_sources[0x1b]	6494	1			T5	2		T7	1		T20	3
valid_sources[0x1c]	5620	1			T2	5		T4	1		T5	3
valid_sources[0x1d]	6554	1			T2	2		T5	1		T7	1
valid_sources[0x1e]	7133	1			T2	3		T20	3		T11	140
valid_sources[0x1f]	5150	1			T20	1		T101	2		T11	140
valid_sources[0x20]	4824	1			T4	2		T5	1		T19	1
valid_sources[0x21]	6978	1			T2	2		T4	1		T17	4
valid_sources[0x22]	5960	1			T2	1		T4	1		T5	1
valid_sources[0x23]	5713	1			T2	2		T4	2		T7	1
valid_sources[0x24]	5610	1			T2	1		T5	1		T7	1
valid_sources[0x25]	5779	1			T4	2		T5	2		T20	1
valid_sources[0x26]	7712	1			T4	1		T5	2		T20	3
valid_sources[0x27]	5737	1			T2	5		T5	1		T9	1
valid_sources[0x28]	6686	1			T5	2		T7	3		T20	1
valid_sources[0x29]	6728	1			T2	3		T5	1		T20	1
valid_sources[0x2a]	5727	1			T5	2		T20	2		T105	4
valid_sources[0x2b]	5553	1			T2	1		T4	1		T5	4
valid_sources[0x2c]	5785	1			T2	2		T5	1		T7	1
valid_sources[0x2d]	5500	1			T2	3		T4	1		T9	2
valid_sources[0x2e]	5417	1			T19	2		T17	4		T20	2
valid_sources[0x2f]	5672	1			T2	1		T4	1		T5	2
valid_sources[0x30]	5215	1			T2	2		T5	1		T9	1
valid_sources[0x31]	5277	1			T2	1		T9	1		T17	5
valid_sources[0x32]	5281	1			T2	4		T7	1		T9	1
valid_sources[0x33]	4925	1			T2	2		T4	1		T20	1
valid_sources[0x34]	5523	1			T2	1		T5	2		T9	2
valid_sources[0x35]	5612	1			T2	2		T5	2		T9	1
valid_sources[0x36]	5968	1			T20	1		T101	1		T11	140
valid_sources[0x37]	5880	1			T2	4		T7	1		T17	2
valid_sources[0x38]	7048	1			T7	1		T9	2		T20	2
valid_sources[0x39]	5024	1			T5	1		T9	1		T101	4
valid_sources[0x3a]	5588	1			T2	1		T4	1		T5	1
valid_sources[0x3b]	5761	1			T4	1		T101	4		T105	2
valid_sources[0x3c]	5577	1			T2	1		T4	1		T5	1
valid_sources[0x3d]	5646	1			T4	1		T5	2		T7	2
valid_sources[0x3e]	6088	1			T2	1		T4	1		T5	6
valid_sources[0x3f]	6470	1			T2	1		T4	2		T5	3
valid_sources[0x40]	6070	1			T2	1		T5	1		T9	1
valid_sources[0x41]	5212	1			T5	1		T9	2		T101	2
valid_sources[0x42]	5339	1			T2	3		T4	1		T101	1
valid_sources[0x43]	6072	1			T4	1		T5	2		T9	7
valid_sources[0x44]	5005	1			T9	2		T101	2		T105	3
valid_sources[0x45]	5392	1			T2	5		T4	1		T5	2
valid_sources[0x46]	5501	1			T2	2		T5	2		T101	2
valid_sources[0x47]	7412	1			T2	2		T5	2		T11	146
valid_sources[0x48]	5924	1			T2	1		T4	1		T5	2
valid_sources[0x49]	5381	1			T2	4		T4	1		T5	2
valid_sources[0x4a]	6670	1			T2	2		T4	2		T5	1
valid_sources[0x4b]	6455	1			T5	1		T9	1		T19	1
valid_sources[0x4c]	5243	1			T4	2		T5	1		T20	1
valid_sources[0x4d]	5912	1			T5	3		T9	1		T20	1
valid_sources[0x4e]	5942	1			T2	1		T5	1		T20	2
valid_sources[0x4f]	5405	1			T2	1		T5	1		T9	1
valid_sources[0x50]	5546	1			T2	3		T9	2		T101	5
valid_sources[0x51]	5703	1			T2	1		T4	3		T19	2
valid_sources[0x52]	5076	1			T2	1		T5	2		T20	1
valid_sources[0x53]	5509	1			T5	2		T9	2		T20	1
valid_sources[0x54]	5062	1			T2	5		T5	1		T19	1
valid_sources[0x55]	5988	1			T2	1		T5	2		T9	1
valid_sources[0x56]	6529	1			T2	2		T4	5		T7	2
valid_sources[0x57]	6848	1			T9	3		T20	3		T101	2
valid_sources[0x58]	5703	1			T2	1		T7	1		T9	3
valid_sources[0x59]	4767	1			T5	1		T9	1		T105	2
valid_sources[0x5a]	6101	1			T7	1		T9	1		T19	2
valid_sources[0x5b]	5927	1			T2	6		T4	1		T20	2
valid_sources[0x5c]	5609	1			T2	1		T5	2		T20	2
valid_sources[0x5d]	5208	1			T2	2		T4	1		T5	4
valid_sources[0x5e]	6603	1			T2	2		T4	1		T5	1
valid_sources[0x5f]	6150	1			T2	4		T5	1		T9	2
valid_sources[0x60]	6334	1			T5	2		T19	1		T17	9
valid_sources[0x61]	6071	1			T4	1		T5	2		T7	1
valid_sources[0x62]	6937	1			T4	1		T5	2		T7	1
valid_sources[0x63]	4918	1			T9	2		T19	1		T20	2
valid_sources[0x64]	6860	1			T9	1		T20	1		T101	1
valid_sources[0x65]	5599	1			T2	3		T4	1		T5	1
valid_sources[0x66]	6379	1			T5	1		T9	2		T20	2
valid_sources[0x67]	6236	1			T2	2		T5	3		T20	1
valid_sources[0x68]	6141	1			T4	1		T5	1		T9	1
valid_sources[0x69]	6396	1			T4	1		T5	1		T7	1
valid_sources[0x6a]	6890	1			T2	3		T9	1		T17	4
valid_sources[0x6b]	6641	1			T2	1		T105	1		T11	148
valid_sources[0x6c]	5571	1			T2	3		T4	2		T101	1
valid_sources[0x6d]	5285	1			T2	3		T4	5		T5	2
valid_sources[0x6e]	6245	1			T4	1		T5	1		T20	1
valid_sources[0x6f]	5575	1			T4	2		T5	1		T9	2
valid_sources[0x70]	5725	1			T5	2		T9	1		T17	1
valid_sources[0x71]	6022	1			T105	2		T31	1		T11	129
valid_sources[0x72]	6624	1			T2	2		T4	1		T5	1
valid_sources[0x73]	5603	1			T5	4		T105	5		T11	135
valid_sources[0x74]	7408	1			T2	5		T5	2		T7	2
valid_sources[0x75]	6315	1			T5	1		T9	5		T20	1
valid_sources[0x76]	5572	1			T2	1		T105	2		T11	172
valid_sources[0x77]	6408	1			T2	2		T4	4		T5	2
valid_sources[0x78]	5745	1			T2	8		T5	1		T7	1
valid_sources[0x79]	5795	1			T2	3		T19	1		T105	3
valid_sources[0x7a]	4839	1			T4	1		T20	2		T11	139
valid_sources[0x7b]	5762	1			T5	4		T7	1		T101	4
valid_sources[0x7c]	5227	1			T2	1		T17	6		T20	3
valid_sources[0x7d]	5618	1			T2	3		T4	1		T5	3
valid_sources[0x7e]	6075	1			T2	6		T5	4		T101	2
valid_sources[0x7f]	5901	1			T9	1		T101	3		T31	2
valid_sources[0x80]	5654	1			T2	1		T4	1		T101	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

363215

1

T2

40

T3

3

T4

16

values[0x0]

all_enables

biggest_size

537896

1

T11

13063

T12

25179

T13

17183

values[0x1]

all_enables

biggest_size

540204

1

T11

13430

T12

25250

T13

17605

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	112804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1106972

1

T3

19

T4

28

T5

61

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	307153	1			T1	1		T3	36		T4	64
values[0x0]	421868	1			T6	6		T25	3		T26	12
values[0x1]	490755	1			T6	2		T26	4		T11	10731

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1168279

1

T3

21

T4

35

T5

79

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4729	1			T3	2		T21	1		T32	1
valid_sources[0x01]	4597	1			T3	1		T35	1		T32	1
valid_sources[0x02]	4372	1			T5	5		T22	1		T11	119
valid_sources[0x03]	4224	1			T11	91		T12	213		T13	166
valid_sources[0x04]	5699	1			T11	97		T12	220		T13	165
valid_sources[0x05]	4670	1			T11	103		T42	1		T12	224
valid_sources[0x06]	4595	1			T4	1		T32	1		T11	102
valid_sources[0x07]	5339	1			T11	88		T57	1		T12	213
valid_sources[0x08]	4092	1			T3	1		T11	114		T42	2
valid_sources[0x09]	5018	1			T5	5		T22	1		T11	94
valid_sources[0x0a]	4814	1			T7	32		T11	98		T57	1
valid_sources[0x0b]	4909	1			T3	1		T11	96		T42	1
valid_sources[0x0c]	4954	1			T11	90		T12	256		T13	137
valid_sources[0x0d]	5207	1			T22	1		T11	108		T12	250
valid_sources[0x0e]	5175	1			T11	117		T12	251		T13	168
valid_sources[0x0f]	4614	1			T11	101		T12	199		T13	155
valid_sources[0x10]	5013	1			T11	121		T34	2		T36	1
valid_sources[0x11]	4956	1			T5	20		T6	1		T17	8
valid_sources[0x12]	4224	1			T11	107		T36	1		T12	201
valid_sources[0x13]	3811	1			T11	104		T12	233		T13	158
valid_sources[0x14]	4233	1			T5	3		T32	1		T11	92
valid_sources[0x15]	4811	1			T11	95		T36	1		T12	228
valid_sources[0x16]	4600	1			T11	111		T36	1		T12	253
valid_sources[0x17]	4269	1			T26	1		T11	113		T12	255
valid_sources[0x18]	4790	1			T35	1		T11	110		T12	241
valid_sources[0x19]	4883	1			T3	1		T11	98		T12	289
valid_sources[0x1a]	4360	1			T4	2		T5	2		T11	117
valid_sources[0x1b]	4686	1			T11	80		T42	1		T12	234
valid_sources[0x1c]	4825	1			T11	100		T12	253		T13	135
valid_sources[0x1d]	5005	1			T22	1		T32	2		T11	96
valid_sources[0x1e]	4834	1			T4	2		T26	1		T11	105
valid_sources[0x1f]	4232	1			T11	97		T12	182		T13	182
valid_sources[0x20]	5039	1			T21	1		T35	2		T11	93
valid_sources[0x21]	5118	1			T6	1		T11	102		T12	241
valid_sources[0x22]	4486	1			T11	109		T12	243		T13	131
valid_sources[0x23]	4328	1			T4	1		T11	100		T12	235
valid_sources[0x24]	4235	1			T11	97		T57	1		T12	222
valid_sources[0x25]	5016	1			T11	98		T57	1		T12	213
valid_sources[0x26]	4890	1			T11	107		T12	257		T13	162
valid_sources[0x27]	4713	1			T11	109		T12	222		T13	150
valid_sources[0x28]	6308	1			T4	1		T32	2		T11	113
valid_sources[0x29]	3871	1			T11	94		T57	1		T12	239
valid_sources[0x2a]	4062	1			T4	1		T5	11		T26	1
valid_sources[0x2b]	5394	1			T11	117		T12	256		T13	161
valid_sources[0x2c]	5068	1			T11	106		T42	1		T57	3
valid_sources[0x2d]	4838	1			T3	2		T4	1		T26	1
valid_sources[0x2e]	5597	1			T11	98		T12	265		T13	129
valid_sources[0x2f]	4426	1			T3	1		T26	2		T11	99
valid_sources[0x30]	4407	1			T22	1		T11	114		T12	188
valid_sources[0x31]	5153	1			T35	3		T11	104		T12	225
valid_sources[0x32]	4521	1			T3	1		T4	1		T11	120
valid_sources[0x33]	6117	1			T11	91		T12	248		T13	150
valid_sources[0x34]	4615	1			T32	1		T11	122		T12	257
valid_sources[0x35]	3859	1			T11	96		T12	253		T13	157
valid_sources[0x36]	5860	1			T3	1		T11	88		T12	251
valid_sources[0x37]	4265	1			T11	88		T12	258		T13	155
valid_sources[0x38]	5270	1			T4	1		T11	118		T12	200
valid_sources[0x39]	5875	1			T11	101		T12	213		T13	181
valid_sources[0x3a]	5367	1			T4	1		T11	105		T42	1
valid_sources[0x3b]	4668	1			T6	1		T11	121		T12	198
valid_sources[0x3c]	4782	1			T11	104		T12	271		T13	168
valid_sources[0x3d]	5208	1			T3	1		T11	95		T12	182
valid_sources[0x3e]	4612	1			T26	1		T11	95		T12	200
valid_sources[0x3f]	4743	1			T3	1		T11	104		T12	257
valid_sources[0x40]	5987	1			T11	97		T12	250		T13	142
valid_sources[0x41]	5099	1			T5	2		T11	113		T12	245
valid_sources[0x42]	4139	1			T5	4		T11	89		T12	248
valid_sources[0x43]	4189	1			T11	90		T12	276		T13	152
valid_sources[0x44]	4623	1			T10	28		T32	1		T11	102
valid_sources[0x45]	4671	1			T35	1		T11	104		T57	1
valid_sources[0x46]	4576	1			T35	1		T11	107		T12	284
valid_sources[0x47]	4340	1			T22	2		T11	98		T12	240
valid_sources[0x48]	4595	1			T35	1		T11	105		T12	250
valid_sources[0x49]	4483	1			T11	87		T12	219		T13	153
valid_sources[0x4a]	4622	1			T5	1		T32	1		T11	95
valid_sources[0x4b]	4116	1			T35	1		T11	79		T36	1
valid_sources[0x4c]	5238	1			T4	1		T35	1		T11	107
valid_sources[0x4d]	4641	1			T11	94		T36	1		T12	236
valid_sources[0x4e]	4748	1			T35	1		T22	1		T11	83
valid_sources[0x4f]	5159	1			T11	114		T12	226		T13	152
valid_sources[0x50]	4892	1			T22	1		T26	1		T11	110
valid_sources[0x51]	4301	1			T11	116		T12	268		T13	148
valid_sources[0x52]	5185	1			T17	22		T11	98		T12	234
valid_sources[0x53]	5074	1			T11	107		T57	2		T12	209
valid_sources[0x54]	4243	1			T11	105		T12	246		T13	144
valid_sources[0x55]	3952	1			T4	4		T35	2		T32	2
valid_sources[0x56]	4447	1			T4	2		T21	1		T11	114
valid_sources[0x57]	4539	1			T32	1		T11	117		T57	2
valid_sources[0x58]	4711	1			T32	1		T11	100		T12	262
valid_sources[0x59]	5208	1			T4	1		T21	1		T11	88
valid_sources[0x5a]	4932	1			T5	14		T32	3		T11	91
valid_sources[0x5b]	4770	1			T26	1		T11	106		T12	227
valid_sources[0x5c]	5229	1			T11	99		T12	255		T13	130
valid_sources[0x5d]	5364	1			T3	1		T4	1		T21	2
valid_sources[0x5e]	4286	1			T11	91		T12	269		T13	163
valid_sources[0x5f]	4914	1			T11	118		T12	242		T13	154
valid_sources[0x60]	5278	1			T11	99		T12	233		T13	158
valid_sources[0x61]	5807	1			T17	12		T22	1		T11	98
valid_sources[0x62]	4760	1			T4	1		T11	108		T12	224
valid_sources[0x63]	4974	1			T4	1		T31	10		T11	97
valid_sources[0x64]	4840	1			T3	2		T11	113		T12	192
valid_sources[0x65]	4364	1			T11	114		T12	235		T13	148
valid_sources[0x66]	4344	1			T17	1		T11	117		T12	227
valid_sources[0x67]	4915	1			T32	2		T11	105		T42	1
valid_sources[0x68]	5692	1			T32	1		T11	88		T42	2
valid_sources[0x69]	4277	1			T3	1		T19	32		T11	98
valid_sources[0x6a]	4438	1			T35	1		T11	109		T57	1
valid_sources[0x6b]	3833	1			T4	2		T17	9		T11	119
valid_sources[0x6c]	4305	1			T22	2		T11	106		T12	211
valid_sources[0x6d]	4752	1			T31	7		T11	106		T57	1
valid_sources[0x6e]	5031	1			T4	1		T11	105		T12	177
valid_sources[0x6f]	4544	1			T4	1		T5	3		T21	1
valid_sources[0x70]	5602	1			T6	1		T35	1		T11	102
valid_sources[0x71]	4749	1			T4	1		T21	1		T11	94
valid_sources[0x72]	5045	1			T4	1		T5	11		T11	102
valid_sources[0x73]	5166	1			T11	103		T36	1		T12	249
valid_sources[0x74]	5332	1			T4	1		T11	118		T12	167
valid_sources[0x75]	5193	1			T11	116		T12	215		T13	173
valid_sources[0x76]	4966	1			T11	94		T12	214		T13	137
valid_sources[0x77]	4984	1			T11	112		T12	242		T13	177
valid_sources[0x78]	5112	1			T6	3		T11	95		T12	262
valid_sources[0x79]	4718	1			T11	112		T12	250		T13	130
valid_sources[0x7a]	4703	1			T21	1		T11	96		T36	2
valid_sources[0x7b]	3959	1			T3	2		T11	107		T42	1
valid_sources[0x7c]	4402	1			T3	2		T4	1		T11	105
valid_sources[0x7d]	4708	1			T35	1		T11	104		T12	241
valid_sources[0x7e]	4933	1			T5	4		T11	84		T12	234
valid_sources[0x7f]	4134	1			T4	1		T11	104		T12	232
valid_sources[0x80]	3950	1			T17	15		T11	92		T12	188

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

280899

1

T3

19

T4

28

T5

61

values[0x0]

all_enables

biggest_size

412860

1

T6

4

T25

2

T26

3

values[0x1]

all_enables

biggest_size

413213

1

T11

8887

T12

20075

T13

13398