Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2638080

1

T2

313

T4

135

T5

256

full_word

1681965

1

T2

40

T3

2

T4

16

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4319765	1			T2	353		T3	2		T4	151
auto[TlIntgErrCmd]	84	1			T59	3		T60	5		T61	9
auto[TlIntgErrData]	108	1			T59	3		T60	8		T61	7
auto[TlIntgErrBoth]	88	1			T59	4		T60	7		T61	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

696847

1

T2

353

T3

2

T4

151

auto[1]

3623198

1

T11

81076

T12

175986

T13

118029

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	298307	1			T2	313		T4	135		T5	256
auto[TlIntgErrNone]	partial	auto[1]	2339520	1			T11	50077		T12	115422		T13	76628
auto[TlIntgErrNone]	full_word	auto[0]	398419	1			T2	40		T3	2		T4	16
auto[TlIntgErrNone]	full_word	auto[1]	1283519	1			T11	30999		T12	60564		T13	41401
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T59	2		T60	2		T61	3
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T59	1		T60	1		T61	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T60	2		T116	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T59	2		T60	4		T61	4
auto[TlIntgErrData]	partial	auto[1]	43	1			T59	1		T60	1		T61	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T60	2		T118	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T60	1		T120	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T59	3		T60	4		T61	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T59	1		T60	3		T61	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	1		T114	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T123	1		T113	1		T124	1