Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3039918

1

T1

94718

T2

250

T3

162944

full_word

1935101

1

T1

58652

T2

32

T3

101365

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4974679	1			T1	153370		T2	282		T3	264309
auto[TlIntgErrCmd]	110	1			T51	4		T52	8		T53	5
auto[TlIntgErrData]	121	1			T51	12		T52	6		T53	8
auto[TlIntgErrBoth]	109	1			T51	4		T52	6		T53	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

791602

1

T1

23833

T2

282

T3

41014

auto[1]

4183417

1

T1

129537

T3

223295

T11

172478

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	333718	1			T1	9919		T2	250		T3	17052
auto[TlIntgErrNone]	partial	auto[1]	2705902	1			T1	84799		T3	145892		T11	112310
auto[TlIntgErrNone]	full_word	auto[0]	457719	1			T1	13914		T2	32		T3	23962
auto[TlIntgErrNone]	full_word	auto[1]	1477340	1			T1	44738		T3	77403		T11	60168
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T51	3		T52	3		T53	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T51	1		T52	5		T53	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T113	1		T109	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T113	1		T109	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T51	5		T52	1		T53	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T51	3		T52	5		T53	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T51	2		T53	1		T116	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T51	2		T53	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T51	2		T52	1		T53	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T51	1		T52	5		T53	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T51	1		T109	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T113	1		T117	1		T118	2