Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72446	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1755851

1

T4

9

T7

6

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	479083	1			T4	92		T7	66		T8	3
values[0x0]	662675	1			T11	13570		T14	49430		T15	51599
values[0x1]	686539	1			T11	14056		T14	51573		T15	53476

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1790827

1

T4

50

T7

37

T8

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7423	1			T11	145		T19	1		T14	482
valid_sources[0x01]	7739	1			T4	1		T10	17		T11	137
valid_sources[0x02]	6822	1			T8	1		T11	156		T17	1
valid_sources[0x03]	7193	1			T11	151		T21	1		T17	1
valid_sources[0x04]	6945	1			T11	149		T17	1		T14	513
valid_sources[0x05]	6925	1			T4	2		T9	25		T11	168
valid_sources[0x06]	6697	1			T4	1		T9	11		T11	149
valid_sources[0x07]	6609	1			T11	145		T99	12		T14	522
valid_sources[0x08]	7018	1			T11	101		T19	1		T17	3
valid_sources[0x09]	6874	1			T11	121		T13	17		T14	497
valid_sources[0x0a]	6760	1			T11	98		T117	1		T14	539
valid_sources[0x0b]	6769	1			T11	94		T14	497		T65	2
valid_sources[0x0c]	7284	1			T11	179		T14	529		T118	6
valid_sources[0x0d]	6692	1			T11	121		T98	4		T99	2
valid_sources[0x0e]	6855	1			T11	145		T17	1		T99	1
valid_sources[0x0f]	8886	1			T11	130		T21	1		T24	6
valid_sources[0x10]	7628	1			T11	130		T98	6		T14	530
valid_sources[0x11]	7502	1			T11	168		T14	537		T65	2
valid_sources[0x12]	6701	1			T11	171		T99	5		T14	536
valid_sources[0x13]	6733	1			T11	120		T17	1		T30	1
valid_sources[0x14]	7744	1			T11	225		T101	16		T99	3
valid_sources[0x15]	6990	1			T11	96		T18	4		T117	3
valid_sources[0x16]	6738	1			T4	1		T11	136		T17	3
valid_sources[0x17]	7347	1			T11	223		T17	1		T101	31
valid_sources[0x18]	6580	1			T10	20		T11	102		T21	2
valid_sources[0x19]	7343	1			T11	110		T21	1		T100	1
valid_sources[0x1a]	6647	1			T11	203		T19	4		T17	1
valid_sources[0x1b]	7268	1			T11	158		T19	5		T17	1
valid_sources[0x1c]	6608	1			T11	104		T19	1		T14	506
valid_sources[0x1d]	7222	1			T11	127		T99	3		T14	548
valid_sources[0x1e]	6779	1			T11	190		T19	2		T21	2
valid_sources[0x1f]	6987	1			T11	141		T17	1		T99	8
valid_sources[0x20]	6742	1			T4	2		T11	132		T17	2
valid_sources[0x21]	6651	1			T11	83		T19	4		T13	11
valid_sources[0x22]	7417	1			T4	1		T11	124		T19	2
valid_sources[0x23]	6802	1			T11	139		T14	539		T66	1
valid_sources[0x24]	7555	1			T11	172		T17	1		T25	1
valid_sources[0x25]	6900	1			T11	129		T99	4		T14	528
valid_sources[0x26]	6668	1			T4	2		T11	163		T98	10
valid_sources[0x27]	7311	1			T11	166		T14	533		T66	4
valid_sources[0x28]	6847	1			T11	137		T14	505		T118	2
valid_sources[0x29]	6971	1			T11	157		T99	8		T14	512
valid_sources[0x2a]	7373	1			T4	2		T10	87		T11	160
valid_sources[0x2b]	6715	1			T11	144		T19	1		T21	1
valid_sources[0x2c]	6684	1			T4	3		T11	139		T18	5
valid_sources[0x2d]	7583	1			T11	158		T19	1		T21	1
valid_sources[0x2e]	6683	1			T11	124		T19	3		T64	7
valid_sources[0x2f]	6858	1			T11	163		T17	2		T14	535
valid_sources[0x30]	7383	1			T11	127		T19	3		T17	1
valid_sources[0x31]	6941	1			T11	193		T45	23		T14	528
valid_sources[0x32]	6597	1			T11	132		T21	1		T14	516
valid_sources[0x33]	7348	1			T11	109		T14	520		T65	1
valid_sources[0x34]	8376	1			T11	154		T12	13		T99	1
valid_sources[0x35]	7120	1			T4	1		T11	120		T17	3
valid_sources[0x36]	7166	1			T11	150		T21	4		T17	1
valid_sources[0x37]	6887	1			T11	166		T99	5		T100	1
valid_sources[0x38]	7298	1			T11	145		T14	489		T65	1
valid_sources[0x39]	7165	1			T11	113		T21	4		T99	1
valid_sources[0x3a]	6830	1			T11	132		T17	1		T14	578
valid_sources[0x3b]	6576	1			T4	1		T11	129		T21	3
valid_sources[0x3c]	6970	1			T11	156		T17	1		T117	4
valid_sources[0x3d]	7126	1			T11	112		T18	6		T14	538
valid_sources[0x3e]	7252	1			T11	141		T14	558		T66	1
valid_sources[0x3f]	6794	1			T4	1		T11	143		T19	2
valid_sources[0x40]	7023	1			T11	145		T19	2		T17	2
valid_sources[0x41]	7003	1			T4	2		T11	103		T14	531
valid_sources[0x42]	6790	1			T11	177		T30	1		T100	3
valid_sources[0x43]	6603	1			T11	100		T17	1		T99	1
valid_sources[0x44]	6815	1			T11	142		T19	1		T18	14
valid_sources[0x45]	6755	1			T11	114		T19	1		T99	4
valid_sources[0x46]	7092	1			T4	1		T11	134		T19	1
valid_sources[0x47]	7111	1			T11	128		T19	1		T18	5
valid_sources[0x48]	8308	1			T11	139		T17	1		T64	9
valid_sources[0x49]	6751	1			T4	1		T11	140		T17	1
valid_sources[0x4a]	7013	1			T4	1		T11	220		T17	1
valid_sources[0x4b]	7036	1			T11	178		T21	2		T117	2
valid_sources[0x4c]	7608	1			T4	2		T11	153		T20	10
valid_sources[0x4d]	7471	1			T11	144		T64	5		T14	549
valid_sources[0x4e]	7093	1			T4	1		T11	129		T12	40
valid_sources[0x4f]	6910	1			T11	195		T17	1		T14	561
valid_sources[0x50]	8569	1			T11	124		T99	1		T30	1
valid_sources[0x51]	7408	1			T11	179		T21	3		T13	19
valid_sources[0x52]	6501	1			T11	118		T17	1		T14	521
valid_sources[0x53]	6807	1			T11	174		T19	1		T99	6
valid_sources[0x54]	8153	1			T4	1		T11	130		T21	1
valid_sources[0x55]	6918	1			T11	140		T19	3		T20	6
valid_sources[0x56]	8500	1			T11	174		T99	1		T14	537
valid_sources[0x57]	7778	1			T11	140		T19	1		T14	523
valid_sources[0x58]	7697	1			T11	161		T19	2		T14	587
valid_sources[0x59]	7469	1			T11	156		T21	1		T14	565
valid_sources[0x5a]	6856	1			T4	1		T11	82		T20	13
valid_sources[0x5b]	7875	1			T11	123		T19	2		T99	7
valid_sources[0x5c]	6817	1			T4	2		T11	165		T99	12
valid_sources[0x5d]	7751	1			T11	105		T19	2		T21	1
valid_sources[0x5e]	7135	1			T11	165		T18	2		T100	2
valid_sources[0x5f]	6599	1			T11	150		T18	7		T99	2
valid_sources[0x60]	6742	1			T11	105		T99	4		T14	580
valid_sources[0x61]	6751	1			T4	1		T11	142		T19	2
valid_sources[0x62]	6957	1			T4	2		T11	206		T19	1
valid_sources[0x63]	7148	1			T11	146		T14	575		T66	1
valid_sources[0x64]	7128	1			T11	148		T21	2		T14	542
valid_sources[0x65]	7415	1			T11	172		T21	2		T13	51
valid_sources[0x66]	6997	1			T11	92		T19	4		T18	9
valid_sources[0x67]	7147	1			T11	148		T19	1		T99	2
valid_sources[0x68]	8634	1			T11	157		T19	1		T17	1
valid_sources[0x69]	7248	1			T11	132		T99	4		T117	1
valid_sources[0x6a]	8620	1			T11	188		T19	2		T14	510
valid_sources[0x6b]	7901	1			T11	81		T99	4		T14	550
valid_sources[0x6c]	7521	1			T4	2		T10	16		T11	137
valid_sources[0x6d]	6910	1			T4	2		T11	169		T117	4
valid_sources[0x6e]	7831	1			T11	143		T14	550		T65	1
valid_sources[0x6f]	8188	1			T11	111		T99	11		T14	517
valid_sources[0x70]	6625	1			T11	163		T14	566		T118	1
valid_sources[0x71]	6868	1			T11	119		T19	1		T18	12
valid_sources[0x72]	7045	1			T11	146		T99	4		T64	3
valid_sources[0x73]	6793	1			T11	99		T14	577		T65	1
valid_sources[0x74]	7093	1			T11	96		T12	20		T18	5
valid_sources[0x75]	6610	1			T11	167		T19	1		T18	9
valid_sources[0x76]	6620	1			T11	178		T14	571		T65	2
valid_sources[0x77]	7413	1			T4	1		T11	147		T19	1
valid_sources[0x78]	6690	1			T4	1		T11	183		T14	555
valid_sources[0x79]	6829	1			T11	170		T18	16		T14	531
valid_sources[0x7a]	7354	1			T11	167		T99	2		T64	1
valid_sources[0x7b]	7016	1			T11	144		T17	1		T14	534
valid_sources[0x7c]	7102	1			T11	105		T19	3		T14	545
valid_sources[0x7d]	6925	1			T4	1		T11	164		T19	1
valid_sources[0x7e]	6837	1			T11	119		T18	9		T117	6
valid_sources[0x7f]	8057	1			T4	1		T11	131		T19	1
valid_sources[0x80]	7862	1			T11	154		T17	1		T99	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

441353

1

T4

9

T7

6

T8

3

values[0x0]

all_enables

biggest_size

657126

1

T11

13444

T14

49026

T15

51175

values[0x1]

all_enables

biggest_size

657372

1

T11

13494

T14

49444

T15

51127

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	134169	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1319594

1

T1

1

T2

1

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	363364	1			T2	1		T3	1		T5	20
values[0x0]	503056	1			T1	4		T11	10091		T23	6
values[0x1]	587343	1			T1	4		T11	11888		T23	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1393573

1

T1

3

T2

1

T5

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5173	1			T11	4		T18	1		T14	421
valid_sources[0x01]	5921	1			T11	348		T17	1		T99	3
valid_sources[0x02]	5396	1			T11	6		T17	1		T14	433
valid_sources[0x03]	5558	1			T11	73		T19	2		T17	1
valid_sources[0x04]	5737	1			T11	225		T22	1		T18	2
valid_sources[0x05]	5821	1			T11	96		T22	1		T14	437
valid_sources[0x06]	5576	1			T11	105		T14	397		T15	449
valid_sources[0x07]	5861	1			T5	1		T11	2		T25	1
valid_sources[0x08]	5798	1			T11	3		T52	1		T99	1
valid_sources[0x09]	5105	1			T11	62		T14	433		T15	461
valid_sources[0x0a]	5951	1			T11	203		T19	1		T18	1
valid_sources[0x0b]	6088	1			T5	1		T11	9		T14	446
valid_sources[0x0c]	5688	1			T11	18		T22	1		T18	1
valid_sources[0x0d]	6671	1			T11	2		T21	1		T99	1
valid_sources[0x0e]	5440	1			T5	1		T11	92		T18	1
valid_sources[0x0f]	5410	1			T11	92		T19	1		T14	424
valid_sources[0x10]	7052	1			T11	469		T21	1		T18	1
valid_sources[0x11]	5334	1			T11	126		T19	1		T14	397
valid_sources[0x12]	5396	1			T11	17		T14	458		T119	1
valid_sources[0x13]	4906	1			T1	1		T11	21		T19	1
valid_sources[0x14]	4742	1			T7	4		T11	27		T21	2
valid_sources[0x15]	5255	1			T11	42		T14	411		T119	1
valid_sources[0x16]	5834	1			T11	316		T18	1		T14	399
valid_sources[0x17]	5902	1			T11	262		T19	1		T24	21
valid_sources[0x18]	5060	1			T11	3		T23	7		T19	1
valid_sources[0x19]	5393	1			T11	192		T22	1		T17	1
valid_sources[0x1a]	5835	1			T11	575		T18	1		T25	1
valid_sources[0x1b]	5397	1			T11	135		T18	1		T14	368
valid_sources[0x1c]	6089	1			T11	51		T17	1		T14	440
valid_sources[0x1d]	5707	1			T11	246		T19	1		T14	431
valid_sources[0x1e]	5721	1			T11	82		T14	391		T15	393
valid_sources[0x1f]	5764	1			T11	14		T99	4		T14	409
valid_sources[0x20]	5510	1			T11	92		T99	4		T14	441
valid_sources[0x21]	6068	1			T5	1		T11	163		T14	421
valid_sources[0x22]	5917	1			T11	152		T30	1		T14	403
valid_sources[0x23]	6217	1			T11	347		T14	431		T67	1
valid_sources[0x24]	5243	1			T11	7		T14	404		T15	422
valid_sources[0x25]	6140	1			T11	230		T17	1		T14	398
valid_sources[0x26]	5007	1			T11	15		T19	1		T14	383
valid_sources[0x27]	5443	1			T11	167		T18	1		T14	443
valid_sources[0x28]	5382	1			T11	91		T14	393		T15	321
valid_sources[0x29]	6214	1			T9	13		T11	412		T27	11
valid_sources[0x2a]	6542	1			T11	78		T18	1		T53	1
valid_sources[0x2b]	4777	1			T11	113		T14	419		T15	391
valid_sources[0x2c]	5773	1			T11	113		T21	3		T14	431
valid_sources[0x2d]	5511	1			T11	8		T18	1		T99	2
valid_sources[0x2e]	6014	1			T11	228		T31	1		T14	440
valid_sources[0x2f]	5205	1			T11	10		T14	413		T15	322
valid_sources[0x30]	6023	1			T11	155		T14	411		T119	1
valid_sources[0x31]	5844	1			T11	108		T18	1		T99	1
valid_sources[0x32]	5519	1			T11	18		T19	1		T14	460
valid_sources[0x33]	5404	1			T11	15		T31	2		T14	404
valid_sources[0x34]	5627	1			T7	2		T11	15		T19	1
valid_sources[0x35]	5690	1			T11	73		T14	442		T15	365
valid_sources[0x36]	6415	1			T11	176		T18	1		T14	407
valid_sources[0x37]	4962	1			T11	201		T21	1		T14	417
valid_sources[0x38]	5766	1			T11	26		T19	1		T14	414
valid_sources[0x39]	5784	1			T11	180		T19	2		T21	1
valid_sources[0x3a]	6219	1			T11	83		T19	1		T99	1
valid_sources[0x3b]	6109	1			T11	3		T19	1		T30	1
valid_sources[0x3c]	6327	1			T11	478		T18	2		T14	407
valid_sources[0x3d]	6661	1			T11	262		T19	1		T18	1
valid_sources[0x3e]	5535	1			T11	5		T14	418		T15	386
valid_sources[0x3f]	5434	1			T11	143		T99	2		T14	384
valid_sources[0x40]	4781	1			T11	4		T14	407		T33	1
valid_sources[0x41]	5778	1			T11	114		T17	1		T18	1
valid_sources[0x42]	5454	1			T11	220		T18	1		T14	398
valid_sources[0x43]	5397	1			T11	20		T19	1		T31	3
valid_sources[0x44]	5111	1			T11	7		T19	1		T99	6
valid_sources[0x45]	5227	1			T11	5		T99	2		T14	399
valid_sources[0x46]	5059	1			T11	11		T19	1		T18	1
valid_sources[0x47]	5100	1			T11	53		T19	1		T18	1
valid_sources[0x48]	7002	1			T11	24		T19	1		T14	446
valid_sources[0x49]	5826	1			T11	6		T19	1		T17	1
valid_sources[0x4a]	5561	1			T11	110		T17	1		T14	429
valid_sources[0x4b]	4703	1			T11	5		T25	2		T14	393
valid_sources[0x4c]	5975	1			T5	1		T11	7		T21	1
valid_sources[0x4d]	5814	1			T11	20		T18	1		T30	1
valid_sources[0x4e]	5949	1			T11	190		T19	2		T14	411
valid_sources[0x4f]	5970	1			T2	1		T5	1		T11	250
valid_sources[0x50]	5184	1			T5	1		T11	82		T17	1
valid_sources[0x51]	5706	1			T11	171		T14	411		T119	2
valid_sources[0x52]	5730	1			T11	60		T19	2		T14	424
valid_sources[0x53]	5156	1			T11	48		T22	1		T19	1
valid_sources[0x54]	5593	1			T11	1		T30	1		T14	424
valid_sources[0x55]	5760	1			T11	85		T14	441		T15	460
valid_sources[0x56]	5336	1			T5	1		T11	10		T14	417
valid_sources[0x57]	5340	1			T11	16		T22	1		T14	404
valid_sources[0x58]	5500	1			T7	1		T11	19		T21	2
valid_sources[0x59]	5669	1			T11	443		T14	412		T15	315
valid_sources[0x5a]	5807	1			T11	2		T30	1		T14	397
valid_sources[0x5b]	6363	1			T11	181		T18	4		T53	3
valid_sources[0x5c]	6569	1			T11	5		T18	3		T14	427
valid_sources[0x5d]	6795	1			T11	6		T18	1		T14	382
valid_sources[0x5e]	5969	1			T11	22		T19	1		T14	390
valid_sources[0x5f]	6276	1			T11	101		T18	3		T14	439
valid_sources[0x60]	5317	1			T11	282		T14	431		T119	1
valid_sources[0x61]	5304	1			T11	183		T18	1		T99	2
valid_sources[0x62]	5645	1			T11	96		T18	2		T14	414
valid_sources[0x63]	5416	1			T11	193		T30	1		T14	388
valid_sources[0x64]	5077	1			T11	11		T22	1		T17	2
valid_sources[0x65]	5591	1			T5	1		T11	14		T30	1
valid_sources[0x66]	5535	1			T11	9		T14	423		T15	395
valid_sources[0x67]	5382	1			T11	132		T99	2		T14	410
valid_sources[0x68]	5125	1			T11	9		T14	418		T15	294
valid_sources[0x69]	5754	1			T11	68		T14	374		T33	2
valid_sources[0x6a]	6052	1			T11	99		T22	1		T53	1
valid_sources[0x6b]	6003	1			T5	1		T11	162		T30	1
valid_sources[0x6c]	5666	1			T7	1		T11	3		T17	1
valid_sources[0x6d]	5290	1			T11	1		T19	1		T18	1
valid_sources[0x6e]	5865	1			T11	16		T99	3		T14	410
valid_sources[0x6f]	5038	1			T5	1		T11	142		T21	3
valid_sources[0x70]	6214	1			T11	254		T99	2		T14	426
valid_sources[0x71]	5663	1			T8	21		T11	240		T18	1
valid_sources[0x72]	5839	1			T11	3		T14	424		T15	352
valid_sources[0x73]	5879	1			T11	30		T14	445		T119	1
valid_sources[0x74]	6224	1			T11	112		T18	1		T14	373
valid_sources[0x75]	5473	1			T11	91		T19	4		T101	10
valid_sources[0x76]	5222	1			T11	27		T19	1		T14	468
valid_sources[0x77]	5548	1			T11	17		T25	1		T14	420
valid_sources[0x78]	6126	1			T11	119		T18	2		T14	428
valid_sources[0x79]	5375	1			T11	20		T14	423		T119	1
valid_sources[0x7a]	5986	1			T11	27		T18	1		T14	425
valid_sources[0x7b]	6354	1			T11	52		T17	1		T18	1
valid_sources[0x7c]	5756	1			T7	3		T11	420		T17	2
valid_sources[0x7d]	5444	1			T11	85		T19	1		T18	2
valid_sources[0x7e]	5665	1			T11	248		T19	3		T14	453
valid_sources[0x7f]	5675	1			T11	288		T14	404		T67	1
valid_sources[0x80]	6002	1			T11	9		T14	427		T15	433

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333670

1

T2

1

T6

1

T7

19

values[0x0]

all_enables

biggest_size

492372

1

T1

1

T11

9914

T23

1

values[0x1]

all_enables

biggest_size

493552

1

T11

10215

T23

1

T27

1