Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3124847

1

T4

83

T7

60

T9

68

full_word

2040722

1

T4

9

T7

6

T8

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5165259	1			T4	92		T7	66		T8	2
auto[TlIntgErrCmd]	114	1			T47	5		T48	8		T49	10
auto[TlIntgErrData]	96	1			T47	7		T48	5		T49	7
auto[TlIntgErrBoth]	100	1			T47	8		T48	7		T49	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

827609

1

T4

92

T7

66

T8

2

auto[1]

4337960

1

T11

85095

T14

316984

T15

339887

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	344485	1			T4	83		T7	60		T9	68
auto[TlIntgErrNone]	partial	auto[1]	2780083	1			T11	53505		T14	200997		T15	218454
auto[TlIntgErrNone]	full_word	auto[0]	482987	1			T4	9		T7	6		T8	2
auto[TlIntgErrNone]	full_word	auto[1]	1557704	1			T11	31590		T14	115987		T15	121433
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T47	3		T48	4		T49	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T48	2		T49	6		T107	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T47	1		T48	1		T49	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T47	1		T48	1		T109	2
auto[TlIntgErrData]	partial	auto[0]	41	1			T47	3		T48	3		T49	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T47	3		T48	2		T49	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T47	1		T111	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T112	1		T113	1		T114	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T47	4		T48	1		T49	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T47	3		T48	6		T49	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T109	1		T105	1		T111	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T47	1		T107	1		T113	1