Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1704647

1

T1

158

T2

89

T3

281

full_word

1094667

1

T1

24

T2

11

T3

26

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2799014	1			T1	182		T2	100		T3	307
auto[TlIntgErrCmd]	90	1			T52	6		T53	4		T54	8
auto[TlIntgErrData]	108	1			T52	9		T53	4		T54	8
auto[TlIntgErrBoth]	102	1			T52	5		T53	2		T54	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

458097

1

T1

182

T2

100

T3

307

auto[1]

2341217

1

T21

423645

T22

275659

T23

73396

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	197903	1			T1	158		T2	89		T3	281
auto[TlIntgErrNone]	partial	auto[1]	1506470	1			T21	272739		T22	175271		T23	47632
auto[TlIntgErrNone]	full_word	auto[0]	260061	1			T1	24		T2	11		T3	26
auto[TlIntgErrNone]	full_word	auto[1]	834580	1			T21	150906		T22	100388		T23	25764
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T53	2		T54	1		T110	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T52	3		T53	2		T54	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T52	2		T114	1		T115	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T52	1		T105	1		T116	2
auto[TlIntgErrData]	partial	auto[0]	53	1			T52	6		T53	1		T54	4
auto[TlIntgErrData]	partial	auto[1]	46	1			T52	2		T53	2		T54	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T52	1		T112	2		T117	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T53	1		T118	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T53	1		T54	2		T110	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T52	4		T54	2		T108	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T118	2		T115	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T52	1		T53	1		T108	2