Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 2636979 1 T1 328 T4 198 T8 77
full_word 1673759 1 T1 29 T4 21 T8 6



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4310488 1 T1 357 T4 219 T8 83
auto[TlIntgErrCmd] 91 1 T54 11 T55 2 T56 2
auto[TlIntgErrData] 65 1 T54 2 T55 6 T56 2
auto[TlIntgErrBoth] 94 1 T54 7 T55 2 T56 6



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 688231 1 T1 357 T4 219 T8 83
auto[1] 3622507 1 T13 155440 T14 433196 T15 592948



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 291796 1 T1 328 T4 198 T8 77
auto[TlIntgErrNone] partial auto[1] 2344958 1 T13 100290 T14 281843 T15 386952
auto[TlIntgErrNone] full_word auto[0] 396316 1 T1 29 T4 21 T8 6
auto[TlIntgErrNone] full_word auto[1] 1277418 1 T13 55150 T14 151353 T15 205996
auto[TlIntgErrCmd] partial auto[0] 30 1 T54 6 T108 3 T113 2
auto[TlIntgErrCmd] partial auto[1] 50 1 T54 5 T55 2 T56 1
auto[TlIntgErrCmd] full_word auto[0] 5 1 T108 2 T111 1 T117 1
auto[TlIntgErrCmd] full_word auto[1] 6 1 T56 1 T108 1 T118 1
auto[TlIntgErrData] partial auto[0] 38 1 T54 2 T55 4 T56 1
auto[TlIntgErrData] partial auto[1] 22 1 T55 2 T108 1 T109 2
auto[TlIntgErrData] full_word auto[0] 3 1 T56 1 T117 1 T112 1
auto[TlIntgErrData] full_word auto[1] 2 1 T111 1 T119 1 - -
auto[TlIntgErrBoth] partial auto[0] 38 1 T54 4 T55 1 T56 2
auto[TlIntgErrBoth] partial auto[1] 47 1 T54 3 T55 1 T56 3
auto[TlIntgErrBoth] full_word auto[0] 5 1 T109 1 T111 1 T119 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T56 1 T108 1 T111 1

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