Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_kmac_cg	100.00	1	100	1	64	64

---

Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_kmac_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00

Variables for Group Instance rom_ctrl_kmac_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_kmac_done	3	0	3	100.00	100	1	1	0
cp_kmac_ready	4	0	4	100.00	100	1	1	0

Summary for Variable cp_kmac_done

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_kmac_done

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
kmac_first	473	1			T3	1		T7	2		T9	2
same_cycle	17	1			T40	1		T42	1		T43	1
rom_first	1106	1			T1	4		T2	1		T4	1

---

Summary for Variable cp_kmac_ready

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_kmac_ready

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stall_repeat	70055580	1			T1	263719		T2	66245		T4	70520
stall_long	7351224	1			T1	27768		T2	6955		T4	7330
stall_1	609896	1			T1	1011		T2	247		T4	172
zero_delay_5	3301064	1			T3	8180		T5	2		T7	16360