Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1997981

1

T1

74

T2

359

T4

198692

full_word

1269292

1

T1

7

T2

33

T4

125600

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3266943	1			T1	81		T2	392		T4	324292
auto[TlIntgErrCmd]	106	1			T62	8		T63	7		T64	5
auto[TlIntgErrData]	110	1			T62	5		T63	6		T64	4
auto[TlIntgErrBoth]	114	1			T62	7		T63	7		T64	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

525129

1

T1

81

T2

392

T4

49998

auto[1]

2742144

1

T4

274294

T22

129390

T23

204484

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	223973	1			T1	74		T2	359		T4	20581
auto[TlIntgErrNone]	partial	auto[1]	1773702	1			T4	178111		T22	83713		T23	132571
auto[TlIntgErrNone]	full_word	auto[0]	301020	1			T1	7		T2	33		T4	29417
auto[TlIntgErrNone]	full_word	auto[1]	968248	1			T4	96183		T22	45677		T23	71913
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T62	3		T63	3		T121	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T62	5		T63	2		T64	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T63	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T63	1		T121	2		T124	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T62	4		T63	3		T64	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T62	1		T63	2		T64	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T118	1		T125	1		T126	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T63	1		T118	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T62	4		T63	2		T64	5
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T62	3		T63	4		T64	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T63	1		T127	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T64	2		T128	1		T125	1