Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.89 92.56 97.67 100.00 98.97 97.45 98.37


Total test records in report: 470
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T304 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2662676923 Jun 22 04:44:55 PM PDT 24 Jun 22 04:45:19 PM PDT 24 8872767673 ps
T305 /workspace/coverage/default/40.rom_ctrl_stress_all.664746702 Jun 22 04:45:46 PM PDT 24 Jun 22 04:47:13 PM PDT 24 41145634448 ps
T306 /workspace/coverage/default/16.rom_ctrl_stress_all.688513793 Jun 22 04:45:04 PM PDT 24 Jun 22 04:45:23 PM PDT 24 2143830143 ps
T307 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3967835998 Jun 22 04:45:07 PM PDT 24 Jun 22 04:45:32 PM PDT 24 9233815610 ps
T308 /workspace/coverage/default/49.rom_ctrl_smoke.2536716567 Jun 22 04:46:04 PM PDT 24 Jun 22 04:46:34 PM PDT 24 3038145045 ps
T309 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3308739386 Jun 22 04:45:14 PM PDT 24 Jun 22 04:45:34 PM PDT 24 6425871843 ps
T310 /workspace/coverage/default/24.rom_ctrl_stress_all.2955253198 Jun 22 04:45:10 PM PDT 24 Jun 22 04:45:48 PM PDT 24 4448206801 ps
T311 /workspace/coverage/default/15.rom_ctrl_stress_all.933629287 Jun 22 04:44:59 PM PDT 24 Jun 22 04:45:29 PM PDT 24 682554786 ps
T312 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2991452710 Jun 22 04:45:07 PM PDT 24 Jun 22 04:49:05 PM PDT 24 32006615323 ps
T313 /workspace/coverage/default/35.rom_ctrl_smoke.1509431644 Jun 22 04:45:31 PM PDT 24 Jun 22 04:45:48 PM PDT 24 2674551517 ps
T314 /workspace/coverage/default/13.rom_ctrl_alert_test.3805330714 Jun 22 04:45:00 PM PDT 24 Jun 22 04:45:16 PM PDT 24 2101092489 ps
T315 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3750069472 Jun 22 04:45:39 PM PDT 24 Jun 22 04:54:34 PM PDT 24 96124278130 ps
T316 /workspace/coverage/default/47.rom_ctrl_stress_all.52989789 Jun 22 04:46:05 PM PDT 24 Jun 22 04:47:11 PM PDT 24 10428646252 ps
T317 /workspace/coverage/default/39.rom_ctrl_stress_all.882506359 Jun 22 04:45:48 PM PDT 24 Jun 22 04:46:37 PM PDT 24 27534024126 ps
T318 /workspace/coverage/default/25.rom_ctrl_smoke.2037171217 Jun 22 04:45:11 PM PDT 24 Jun 22 04:45:42 PM PDT 24 12100016476 ps
T319 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2608752263 Jun 22 04:44:55 PM PDT 24 Jun 22 04:46:06 PM PDT 24 2944891061 ps
T111 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2161854602 Jun 22 04:45:53 PM PDT 24 Jun 22 05:44:37 PM PDT 24 80931239972 ps
T320 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.192015624 Jun 22 04:45:00 PM PDT 24 Jun 22 04:47:03 PM PDT 24 32023449480 ps
T321 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3085437118 Jun 22 04:45:53 PM PDT 24 Jun 22 04:46:00 PM PDT 24 435873988 ps
T322 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.730942195 Jun 22 04:45:11 PM PDT 24 Jun 22 04:45:39 PM PDT 24 3108929525 ps
T323 /workspace/coverage/default/17.rom_ctrl_stress_all.3654422483 Jun 22 04:45:08 PM PDT 24 Jun 22 04:45:31 PM PDT 24 2755032829 ps
T324 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.407911083 Jun 22 04:44:50 PM PDT 24 Jun 22 04:47:57 PM PDT 24 35243988863 ps
T325 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.541911189 Jun 22 04:45:32 PM PDT 24 Jun 22 04:45:59 PM PDT 24 11585774123 ps
T326 /workspace/coverage/default/36.rom_ctrl_smoke.916799982 Jun 22 04:45:40 PM PDT 24 Jun 22 04:46:18 PM PDT 24 13873592712 ps
T327 /workspace/coverage/default/28.rom_ctrl_stress_all.2973103842 Jun 22 04:45:17 PM PDT 24 Jun 22 04:45:36 PM PDT 24 2729996430 ps
T328 /workspace/coverage/default/48.rom_ctrl_stress_all.3146185285 Jun 22 04:46:02 PM PDT 24 Jun 22 04:46:42 PM PDT 24 2981659427 ps
T329 /workspace/coverage/default/1.rom_ctrl_smoke.3103146265 Jun 22 04:44:42 PM PDT 24 Jun 22 04:45:14 PM PDT 24 4092867609 ps
T330 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3739278770 Jun 22 04:45:11 PM PDT 24 Jun 22 04:45:24 PM PDT 24 342260718 ps
T331 /workspace/coverage/default/42.rom_ctrl_smoke.382465898 Jun 22 04:45:46 PM PDT 24 Jun 22 04:46:01 PM PDT 24 1498405772 ps
T332 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.4023973027 Jun 22 04:45:45 PM PDT 24 Jun 22 05:22:18 PM PDT 24 55952188744 ps
T333 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1081138633 Jun 22 04:45:23 PM PDT 24 Jun 22 04:45:37 PM PDT 24 5987676273 ps
T334 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2605176281 Jun 22 04:45:47 PM PDT 24 Jun 22 04:47:56 PM PDT 24 2167989035 ps
T335 /workspace/coverage/default/27.rom_ctrl_alert_test.1714573394 Jun 22 04:45:11 PM PDT 24 Jun 22 04:45:23 PM PDT 24 4752308702 ps
T336 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2115097558 Jun 22 04:44:46 PM PDT 24 Jun 22 04:44:52 PM PDT 24 1322304448 ps
T337 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2665953897 Jun 22 04:46:04 PM PDT 24 Jun 22 04:46:10 PM PDT 24 391267503 ps
T338 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.858125627 Jun 22 04:44:42 PM PDT 24 Jun 22 04:45:09 PM PDT 24 4361399251 ps
T339 /workspace/coverage/default/23.rom_ctrl_stress_all.113099941 Jun 22 04:45:07 PM PDT 24 Jun 22 04:45:24 PM PDT 24 6143799552 ps
T340 /workspace/coverage/default/28.rom_ctrl_smoke.977740805 Jun 22 04:45:12 PM PDT 24 Jun 22 04:45:46 PM PDT 24 21250408241 ps
T341 /workspace/coverage/default/49.rom_ctrl_stress_all.2061866923 Jun 22 04:46:01 PM PDT 24 Jun 22 04:47:22 PM PDT 24 8956378622 ps
T342 /workspace/coverage/default/24.rom_ctrl_alert_test.3011760767 Jun 22 04:45:11 PM PDT 24 Jun 22 04:45:21 PM PDT 24 3192116551 ps
T343 /workspace/coverage/default/20.rom_ctrl_alert_test.3888175059 Jun 22 04:45:07 PM PDT 24 Jun 22 04:45:21 PM PDT 24 1510669004 ps
T344 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4047981988 Jun 22 04:45:39 PM PDT 24 Jun 22 04:46:00 PM PDT 24 1479115977 ps
T345 /workspace/coverage/default/37.rom_ctrl_smoke.4053959580 Jun 22 04:45:44 PM PDT 24 Jun 22 04:46:17 PM PDT 24 4455721534 ps
T346 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2929893456 Jun 22 04:45:55 PM PDT 24 Jun 22 04:46:22 PM PDT 24 4572163186 ps
T347 /workspace/coverage/default/44.rom_ctrl_alert_test.1343854232 Jun 22 04:45:54 PM PDT 24 Jun 22 04:46:07 PM PDT 24 2621911421 ps
T348 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.419337607 Jun 22 04:45:03 PM PDT 24 Jun 22 05:01:59 PM PDT 24 53535122948 ps
T349 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.126025781 Jun 22 04:45:11 PM PDT 24 Jun 22 04:45:28 PM PDT 24 3814175317 ps
T44 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3645968354 Jun 22 04:45:54 PM PDT 24 Jun 22 05:18:16 PM PDT 24 208191599203 ps
T350 /workspace/coverage/default/32.rom_ctrl_smoke.1477646720 Jun 22 04:45:25 PM PDT 24 Jun 22 04:45:43 PM PDT 24 5198130385 ps
T351 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1536082746 Jun 22 04:45:53 PM PDT 24 Jun 22 04:46:05 PM PDT 24 13037903405 ps
T352 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.251278207 Jun 22 04:45:52 PM PDT 24 Jun 22 04:49:33 PM PDT 24 93438286118 ps
T353 /workspace/coverage/default/40.rom_ctrl_smoke.1000016051 Jun 22 04:45:45 PM PDT 24 Jun 22 04:46:05 PM PDT 24 5169241550 ps
T354 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2707666735 Jun 22 04:45:25 PM PDT 24 Jun 22 04:49:29 PM PDT 24 83744181694 ps
T355 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.310626003 Jun 22 04:44:51 PM PDT 24 Jun 22 04:49:43 PM PDT 24 101112946127 ps
T356 /workspace/coverage/default/19.rom_ctrl_alert_test.4099538970 Jun 22 04:45:07 PM PDT 24 Jun 22 04:45:20 PM PDT 24 2746109117 ps
T110 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1233798016 Jun 22 04:45:05 PM PDT 24 Jun 22 05:34:00 PM PDT 24 158613365427 ps
T27 /workspace/coverage/default/2.rom_ctrl_sec_cm.14560591 Jun 22 04:44:40 PM PDT 24 Jun 22 04:45:39 PM PDT 24 4135351708 ps
T357 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.872741496 Jun 22 04:44:40 PM PDT 24 Jun 22 04:44:59 PM PDT 24 1226930138 ps
T358 /workspace/coverage/default/0.rom_ctrl_smoke.2165654242 Jun 22 04:44:41 PM PDT 24 Jun 22 04:44:56 PM PDT 24 683504017 ps
T359 /workspace/coverage/default/45.rom_ctrl_alert_test.3166293205 Jun 22 04:45:54 PM PDT 24 Jun 22 04:46:03 PM PDT 24 5649114848 ps
T360 /workspace/coverage/default/33.rom_ctrl_alert_test.3196079924 Jun 22 04:45:32 PM PDT 24 Jun 22 04:45:49 PM PDT 24 1932417752 ps
T361 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3414475609 Jun 22 04:45:52 PM PDT 24 Jun 22 04:46:27 PM PDT 24 19189163742 ps
T362 /workspace/coverage/default/11.rom_ctrl_stress_all.380671724 Jun 22 04:44:56 PM PDT 24 Jun 22 04:45:12 PM PDT 24 309143790 ps
T363 /workspace/coverage/default/11.rom_ctrl_smoke.2293294578 Jun 22 04:45:02 PM PDT 24 Jun 22 04:45:12 PM PDT 24 190717410 ps
T364 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4121879992 Jun 22 04:45:19 PM PDT 24 Jun 22 04:45:41 PM PDT 24 7833759452 ps
T365 /workspace/coverage/default/14.rom_ctrl_smoke.3957644411 Jun 22 04:45:02 PM PDT 24 Jun 22 04:45:17 PM PDT 24 687113389 ps
T366 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2941240879 Jun 22 04:45:11 PM PDT 24 Jun 22 05:27:26 PM PDT 24 116386820413 ps
T367 /workspace/coverage/default/8.rom_ctrl_stress_all.3980676301 Jun 22 04:44:50 PM PDT 24 Jun 22 04:45:00 PM PDT 24 114194954 ps
T368 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.137694381 Jun 22 04:46:03 PM PDT 24 Jun 22 04:48:57 PM PDT 24 78682130216 ps
T369 /workspace/coverage/default/38.rom_ctrl_smoke.3368977841 Jun 22 04:45:39 PM PDT 24 Jun 22 04:46:13 PM PDT 24 3871091562 ps
T370 /workspace/coverage/default/32.rom_ctrl_stress_all.3034534797 Jun 22 04:45:26 PM PDT 24 Jun 22 04:45:48 PM PDT 24 3822322977 ps
T371 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1330733367 Jun 22 04:45:16 PM PDT 24 Jun 22 04:47:31 PM PDT 24 34822395440 ps
T372 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.477835284 Jun 22 04:46:09 PM PDT 24 Jun 22 04:46:38 PM PDT 24 2949366040 ps
T373 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.984971594 Jun 22 04:46:00 PM PDT 24 Jun 22 04:59:48 PM PDT 24 28083831297 ps
T374 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.142667969 Jun 22 04:45:09 PM PDT 24 Jun 22 04:45:17 PM PDT 24 611328574 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3132777700 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:37 PM PDT 24 4350346786 ps
T64 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1958194474 Jun 22 04:32:10 PM PDT 24 Jun 22 04:32:14 PM PDT 24 348156630 ps
T65 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.451627702 Jun 22 04:32:21 PM PDT 24 Jun 22 04:33:30 PM PDT 24 9403000687 ps
T61 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.325279637 Jun 22 04:32:16 PM PDT 24 Jun 22 04:32:53 PM PDT 24 684120307 ps
T376 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3970561840 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:54 PM PDT 24 4870100760 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.400338222 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:40 PM PDT 24 25875600346 ps
T70 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.760530312 Jun 22 04:32:23 PM PDT 24 Jun 22 04:32:33 PM PDT 24 3150229239 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4079286309 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:33 PM PDT 24 6245928280 ps
T71 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2670172298 Jun 22 04:32:36 PM PDT 24 Jun 22 04:32:47 PM PDT 24 2447827939 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1044432371 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:33 PM PDT 24 7937626780 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1272584707 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:29 PM PDT 24 3960788598 ps
T62 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1946709987 Jun 22 04:32:26 PM PDT 24 Jun 22 04:33:42 PM PDT 24 6615024949 ps
T100 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2161013503 Jun 22 04:32:28 PM PDT 24 Jun 22 04:32:43 PM PDT 24 1461357606 ps
T106 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.775027842 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:32 PM PDT 24 90102185 ps
T63 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.434157574 Jun 22 04:32:33 PM PDT 24 Jun 22 04:33:12 PM PDT 24 242357183 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.149726903 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:40 PM PDT 24 191108685 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1307797558 Jun 22 04:32:31 PM PDT 24 Jun 22 04:32:38 PM PDT 24 174884425 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3381526072 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:51 PM PDT 24 1264996705 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1958004326 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:55 PM PDT 24 20534985146 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3782847669 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:33 PM PDT 24 5378553370 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.5474219 Jun 22 04:32:32 PM PDT 24 Jun 22 04:32:45 PM PDT 24 1545233315 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.451356206 Jun 22 04:32:29 PM PDT 24 Jun 22 04:32:40 PM PDT 24 3507850822 ps
T74 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4079612167 Jun 22 04:32:14 PM PDT 24 Jun 22 04:32:33 PM PDT 24 1944757381 ps
T75 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3453508389 Jun 22 04:32:36 PM PDT 24 Jun 22 04:34:14 PM PDT 24 30521209937 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2716314899 Jun 22 04:32:25 PM PDT 24 Jun 22 04:33:00 PM PDT 24 26463830376 ps
T116 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3671734252 Jun 22 04:32:25 PM PDT 24 Jun 22 04:33:13 PM PDT 24 4458474689 ps
T383 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2536853281 Jun 22 04:32:29 PM PDT 24 Jun 22 04:32:44 PM PDT 24 10463320169 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1148214206 Jun 22 04:32:36 PM PDT 24 Jun 22 04:32:47 PM PDT 24 217231038 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.112473217 Jun 22 04:32:09 PM PDT 24 Jun 22 04:33:25 PM PDT 24 1460650584 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.259851946 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:38 PM PDT 24 1645734924 ps
T76 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1863819616 Jun 22 04:32:32 PM PDT 24 Jun 22 04:33:02 PM PDT 24 6964813835 ps
T113 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2338571982 Jun 22 04:32:30 PM PDT 24 Jun 22 04:33:41 PM PDT 24 651212382 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.618609122 Jun 22 04:32:25 PM PDT 24 Jun 22 04:32:35 PM PDT 24 4129232132 ps
T386 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2886436478 Jun 22 04:32:31 PM PDT 24 Jun 22 04:32:49 PM PDT 24 1857499603 ps
T77 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.440907486 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:36 PM PDT 24 506431787 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3386134014 Jun 22 04:32:34 PM PDT 24 Jun 22 04:33:03 PM PDT 24 546210098 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.540344375 Jun 22 04:32:20 PM PDT 24 Jun 22 04:32:31 PM PDT 24 2109457934 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2181311937 Jun 22 04:32:32 PM PDT 24 Jun 22 04:32:41 PM PDT 24 775217567 ps
T87 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3576379570 Jun 22 04:32:28 PM PDT 24 Jun 22 04:34:04 PM PDT 24 50442777534 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1675290783 Jun 22 04:32:20 PM PDT 24 Jun 22 04:32:30 PM PDT 24 811110846 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1485796330 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:36 PM PDT 24 361617723 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2757591021 Jun 22 04:32:12 PM PDT 24 Jun 22 04:32:24 PM PDT 24 4434628321 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.23238482 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:41 PM PDT 24 2302876028 ps
T105 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1181145604 Jun 22 04:32:33 PM PDT 24 Jun 22 04:32:43 PM PDT 24 2160033179 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.93151717 Jun 22 04:32:09 PM PDT 24 Jun 22 04:32:28 PM PDT 24 3231878131 ps
T119 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.857088851 Jun 22 04:32:27 PM PDT 24 Jun 22 04:33:04 PM PDT 24 1507614878 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2699697673 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:30 PM PDT 24 3555903517 ps
T392 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4142063678 Jun 22 04:32:26 PM PDT 24 Jun 22 04:34:01 PM PDT 24 108658305644 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2929479912 Jun 22 04:32:13 PM PDT 24 Jun 22 04:32:27 PM PDT 24 1518439154 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2878274712 Jun 22 04:32:09 PM PDT 24 Jun 22 04:32:17 PM PDT 24 467731169 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.558895806 Jun 22 04:32:18 PM PDT 24 Jun 22 04:32:37 PM PDT 24 8567996834 ps
T395 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.243855672 Jun 22 04:32:30 PM PDT 24 Jun 22 04:33:17 PM PDT 24 13029138296 ps
T90 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.507844182 Jun 22 04:32:33 PM PDT 24 Jun 22 04:33:37 PM PDT 24 34915904038 ps
T396 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4032423715 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:39 PM PDT 24 1107451192 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1912112444 Jun 22 04:32:32 PM PDT 24 Jun 22 04:32:37 PM PDT 24 459918469 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.922664809 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:35 PM PDT 24 292906852 ps
T399 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4157743566 Jun 22 04:32:35 PM PDT 24 Jun 22 04:32:43 PM PDT 24 201560320 ps
T400 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.215093532 Jun 22 04:32:30 PM PDT 24 Jun 22 04:32:44 PM PDT 24 1449186103 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2122542071 Jun 22 04:32:33 PM PDT 24 Jun 22 04:32:49 PM PDT 24 3226120464 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.27080055 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:35 PM PDT 24 5204473758 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1667243174 Jun 22 04:32:18 PM PDT 24 Jun 22 04:32:25 PM PDT 24 102524923 ps
T114 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3495975383 Jun 22 04:32:20 PM PDT 24 Jun 22 04:33:30 PM PDT 24 584882251 ps
T115 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3987117497 Jun 22 04:32:20 PM PDT 24 Jun 22 04:33:34 PM PDT 24 627403153 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1946236156 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:32 PM PDT 24 1150441891 ps
T120 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1526817322 Jun 22 04:32:18 PM PDT 24 Jun 22 04:33:30 PM PDT 24 1129066048 ps
T405 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3528302315 Jun 22 04:32:21 PM PDT 24 Jun 22 04:32:36 PM PDT 24 3040114147 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2470404252 Jun 22 04:32:30 PM PDT 24 Jun 22 04:32:57 PM PDT 24 2361425095 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.324165735 Jun 22 04:32:20 PM PDT 24 Jun 22 04:32:37 PM PDT 24 8938748419 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1758951994 Jun 22 04:32:33 PM PDT 24 Jun 22 04:32:42 PM PDT 24 2777672919 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.150277401 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:24 PM PDT 24 182278780 ps
T123 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1167033349 Jun 22 04:32:28 PM PDT 24 Jun 22 04:33:38 PM PDT 24 246613822 ps
T121 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1334702241 Jun 22 04:32:28 PM PDT 24 Jun 22 04:33:43 PM PDT 24 6258866730 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1710530988 Jun 22 04:32:14 PM PDT 24 Jun 22 04:32:21 PM PDT 24 307343071 ps
T95 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1776983209 Jun 22 04:32:18 PM PDT 24 Jun 22 04:32:55 PM PDT 24 3264052496 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.881977977 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:38 PM PDT 24 949090913 ps
T412 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2056164619 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:50 PM PDT 24 18653304746 ps
T413 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3665359749 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:41 PM PDT 24 227156842 ps
T96 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3970611945 Jun 22 04:32:21 PM PDT 24 Jun 22 04:32:58 PM PDT 24 2830037893 ps
T117 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.774792930 Jun 22 04:32:26 PM PDT 24 Jun 22 04:33:36 PM PDT 24 238605621 ps
T414 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.678913525 Jun 22 04:32:30 PM PDT 24 Jun 22 04:32:38 PM PDT 24 1906801496 ps
T415 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3414065560 Jun 22 04:32:30 PM PDT 24 Jun 22 04:32:42 PM PDT 24 2069247154 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.269213318 Jun 22 04:32:11 PM PDT 24 Jun 22 04:32:40 PM PDT 24 565966784 ps
T416 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3424528153 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:51 PM PDT 24 1308136083 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1605284042 Jun 22 04:32:12 PM PDT 24 Jun 22 04:32:28 PM PDT 24 1755294880 ps
T418 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4171932742 Jun 22 04:32:25 PM PDT 24 Jun 22 04:33:45 PM PDT 24 8977289044 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1565682143 Jun 22 04:32:28 PM PDT 24 Jun 22 04:32:34 PM PDT 24 93691378 ps
T420 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2370842297 Jun 22 04:32:26 PM PDT 24 Jun 22 04:32:36 PM PDT 24 2204098567 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.189825337 Jun 22 04:32:10 PM PDT 24 Jun 22 04:32:23 PM PDT 24 6107412849 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4274492759 Jun 22 04:32:11 PM PDT 24 Jun 22 04:32:25 PM PDT 24 1032812484 ps
T423 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2236444253 Jun 22 04:32:30 PM PDT 24 Jun 22 04:33:21 PM PDT 24 20131793167 ps
T424 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2380758336 Jun 22 04:32:28 PM PDT 24 Jun 22 04:32:33 PM PDT 24 381240656 ps
T425 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3770936714 Jun 22 04:32:29 PM PDT 24 Jun 22 04:32:45 PM PDT 24 1931443822 ps
T426 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.977368329 Jun 22 04:32:31 PM PDT 24 Jun 22 04:32:49 PM PDT 24 3585265685 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1021986908 Jun 22 04:32:16 PM PDT 24 Jun 22 04:32:34 PM PDT 24 2040435112 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3616045944 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:32 PM PDT 24 1325226845 ps
T429 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4261221581 Jun 22 04:32:30 PM PDT 24 Jun 22 04:32:46 PM PDT 24 1392899245 ps
T430 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3299626173 Jun 22 04:32:28 PM PDT 24 Jun 22 04:32:37 PM PDT 24 592510705 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1037989730 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:29 PM PDT 24 730992489 ps
T118 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2876711851 Jun 22 04:32:37 PM PDT 24 Jun 22 04:33:19 PM PDT 24 772689563 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1788303013 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:28 PM PDT 24 6046849775 ps
T91 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2401776719 Jun 22 04:32:30 PM PDT 24 Jun 22 04:33:19 PM PDT 24 10976147576 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2871659972 Jun 22 04:32:11 PM PDT 24 Jun 22 04:32:26 PM PDT 24 1877147332 ps
T122 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1924394279 Jun 22 04:32:27 PM PDT 24 Jun 22 04:33:40 PM PDT 24 9270582824 ps
T99 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3762013837 Jun 22 04:32:34 PM PDT 24 Jun 22 04:33:09 PM PDT 24 1040762725 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1109963951 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:41 PM PDT 24 1213327151 ps
T434 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2055856761 Jun 22 04:32:37 PM PDT 24 Jun 22 04:33:57 PM PDT 24 3335566033 ps
T435 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1434226037 Jun 22 04:32:28 PM PDT 24 Jun 22 04:33:29 PM PDT 24 11502274781 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.727137612 Jun 22 04:32:11 PM PDT 24 Jun 22 04:32:20 PM PDT 24 818549637 ps
T437 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3271522901 Jun 22 04:33:43 PM PDT 24 Jun 22 04:34:02 PM PDT 24 1889917924 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2913658150 Jun 22 04:32:25 PM PDT 24 Jun 22 04:32:37 PM PDT 24 1157772293 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1504761434 Jun 22 04:32:28 PM PDT 24 Jun 22 04:32:39 PM PDT 24 1151483599 ps
T440 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2084276287 Jun 22 04:32:18 PM PDT 24 Jun 22 04:32:24 PM PDT 24 4959867265 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3124028789 Jun 22 04:32:10 PM PDT 24 Jun 22 04:32:16 PM PDT 24 341405790 ps
T442 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2714928652 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:53 PM PDT 24 5207930804 ps
T443 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.209216957 Jun 22 04:32:30 PM PDT 24 Jun 22 04:32:37 PM PDT 24 190994898 ps
T444 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1462409631 Jun 22 04:32:34 PM PDT 24 Jun 22 04:33:45 PM PDT 24 238138855 ps
T445 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3234751726 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:50 PM PDT 24 7888663025 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.393787575 Jun 22 04:32:10 PM PDT 24 Jun 22 04:32:15 PM PDT 24 174680092 ps
T447 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2936672416 Jun 22 04:32:30 PM PDT 24 Jun 22 04:32:43 PM PDT 24 5547794018 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2751401111 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:26 PM PDT 24 90167781 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1664485567 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:31 PM PDT 24 2141126015 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.26162801 Jun 22 04:32:13 PM PDT 24 Jun 22 04:32:57 PM PDT 24 18374237489 ps
T451 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4039099497 Jun 22 04:32:26 PM PDT 24 Jun 22 04:32:32 PM PDT 24 169832971 ps
T452 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3861135823 Jun 22 04:32:27 PM PDT 24 Jun 22 04:32:38 PM PDT 24 626659059 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.635576268 Jun 22 04:32:21 PM PDT 24 Jun 22 04:32:32 PM PDT 24 5590346078 ps
T453 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.250033902 Jun 22 04:32:35 PM PDT 24 Jun 22 04:32:51 PM PDT 24 3087579058 ps
T454 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2955695422 Jun 22 04:32:26 PM PDT 24 Jun 22 04:32:36 PM PDT 24 3005413712 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2690354648 Jun 22 04:32:23 PM PDT 24 Jun 22 04:32:37 PM PDT 24 6246525818 ps
T456 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1090146870 Jun 22 04:32:26 PM PDT 24 Jun 22 04:32:41 PM PDT 24 1829549085 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2897315421 Jun 22 04:32:27 PM PDT 24 Jun 22 04:33:28 PM PDT 24 27767809187 ps
T457 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4253309900 Jun 22 04:32:27 PM PDT 24 Jun 22 04:33:12 PM PDT 24 1346848254 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2513790479 Jun 22 04:32:14 PM PDT 24 Jun 22 04:32:28 PM PDT 24 2751795582 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2823951536 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:35 PM PDT 24 2083495194 ps
T460 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1415284312 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:34 PM PDT 24 1664824713 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1133894942 Jun 22 04:32:23 PM PDT 24 Jun 22 04:33:46 PM PDT 24 46997174376 ps
T462 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3800895978 Jun 22 04:32:11 PM PDT 24 Jun 22 04:32:30 PM PDT 24 3327839730 ps
T463 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1950707646 Jun 22 04:32:10 PM PDT 24 Jun 22 04:32:16 PM PDT 24 86640184 ps
T464 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.305879847 Jun 22 04:32:25 PM PDT 24 Jun 22 04:32:37 PM PDT 24 1195652419 ps
T465 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3827403321 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:48 PM PDT 24 1537856473 ps
T466 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1194620138 Jun 22 04:32:28 PM PDT 24 Jun 22 04:32:45 PM PDT 24 7810423224 ps
T467 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1018232313 Jun 22 04:32:21 PM PDT 24 Jun 22 04:32:31 PM PDT 24 663231793 ps
T468 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3235674708 Jun 22 04:32:29 PM PDT 24 Jun 22 04:32:39 PM PDT 24 166105214 ps
T469 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3256735679 Jun 22 04:32:19 PM PDT 24 Jun 22 04:32:29 PM PDT 24 334557257 ps
T98 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.734258840 Jun 22 04:32:18 PM PDT 24 Jun 22 04:32:25 PM PDT 24 1036826047 ps
T470 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2913896854 Jun 22 04:32:20 PM PDT 24 Jun 22 04:32:36 PM PDT 24 3657733790 ps

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.426429505
Short name T9
Test name
Test status
Simulation time 151627196242 ps
CPU time 326.15 seconds
Started Jun 22 04:45:01 PM PDT 24
Finished Jun 22 04:50:27 PM PDT 24
Peak memory 224604 kb
Host smart-0bf367a0-5225-4f59-92a8-530d5746e4ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426429505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.426429505
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1160680860
Short name T22
Test name
Test status
Simulation time 97066949894 ps
CPU time 2637.71 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 05:29:15 PM PDT 24
Peak memory 248128 kb
Host smart-dfd6eb52-c584-4ad8-a2a4-b1a48d4bb51c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160680860 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1160680860
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1430756486
Short name T1
Test name
Test status
Simulation time 619920967 ps
CPU time 19.08 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 04:46:14 PM PDT 24
Peak memory 215100 kb
Host smart-3fc652a3-b6d4-4c30-929d-1ba0e30cd1e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430756486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1430756486
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1357452198
Short name T16
Test name
Test status
Simulation time 18443126291 ps
CPU time 201.8 seconds
Started Jun 22 04:44:39 PM PDT 24
Finished Jun 22 04:48:02 PM PDT 24
Peak memory 236932 kb
Host smart-f75b68c7-7f1b-4d8b-a26b-b646bc17df6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357452198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1357452198
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1946709987
Short name T62
Test name
Test status
Simulation time 6615024949 ps
CPU time 75.41 seconds
Started Jun 22 04:32:26 PM PDT 24
Finished Jun 22 04:33:42 PM PDT 24
Peak memory 219600 kb
Host smart-e12879da-ca63-46f2-9648-41bf4457847e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946709987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1946709987
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1728776219
Short name T17
Test name
Test status
Simulation time 316188620 ps
CPU time 101.33 seconds
Started Jun 22 04:44:38 PM PDT 24
Finished Jun 22 04:46:20 PM PDT 24
Peak memory 237688 kb
Host smart-ae07e034-2b06-40bb-ab17-f5ce7c44eb5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728776219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1728776219
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3735038949
Short name T59
Test name
Test status
Simulation time 11393307350 ps
CPU time 37.1 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:46:31 PM PDT 24
Peak memory 213744 kb
Host smart-a14a5b3a-25c8-4ab9-8440-e2f33b1b8f1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735038949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3735038949
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1526817322
Short name T120
Test name
Test status
Simulation time 1129066048 ps
CPU time 71.39 seconds
Started Jun 22 04:32:18 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 219472 kb
Host smart-4456e80d-0ced-43a9-90fe-1c8440f4d9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526817322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1526817322
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.760530312
Short name T70
Test name
Test status
Simulation time 3150229239 ps
CPU time 9.35 seconds
Started Jun 22 04:32:23 PM PDT 24
Finished Jun 22 04:32:33 PM PDT 24
Peak memory 211360 kb
Host smart-32b22a7f-cc9a-4ac2-872f-24fb0cb59356
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760530312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.760530312
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3551722901
Short name T43
Test name
Test status
Simulation time 219976649040 ps
CPU time 2222.8 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 05:22:57 PM PDT 24
Peak memory 238676 kb
Host smart-068e9fe6-3c9f-47b7-9318-a0d3d52244ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551722901 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3551722901
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3726309532
Short name T68
Test name
Test status
Simulation time 11634773353 ps
CPU time 13.3 seconds
Started Jun 22 04:44:39 PM PDT 24
Finished Jun 22 04:44:53 PM PDT 24
Peak memory 211096 kb
Host smart-9d9eb657-61d2-4660-923b-8e0c2c51ccc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726309532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3726309532
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4063565007
Short name T25
Test name
Test status
Simulation time 3566472152 ps
CPU time 30.43 seconds
Started Jun 22 04:44:56 PM PDT 24
Finished Jun 22 04:45:26 PM PDT 24
Peak memory 211768 kb
Host smart-8a74584b-db14-44be-8dd4-22e74c0ea2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063565007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4063565007
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2183480333
Short name T205
Test name
Test status
Simulation time 979518816 ps
CPU time 9.46 seconds
Started Jun 22 04:44:59 PM PDT 24
Finished Jun 22 04:45:09 PM PDT 24
Peak memory 212244 kb
Host smart-bea2f07b-e507-4cca-a6d5-953175851f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183480333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2183480333
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.631394327
Short name T49
Test name
Test status
Simulation time 3103003185 ps
CPU time 11.38 seconds
Started Jun 22 04:45:31 PM PDT 24
Finished Jun 22 04:45:43 PM PDT 24
Peak memory 211880 kb
Host smart-3b708db8-41f5-4c80-9ddb-f87f0c25787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631394327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.631394327
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3762013837
Short name T99
Test name
Test status
Simulation time 1040762725 ps
CPU time 34.07 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:33:09 PM PDT 24
Peak memory 211296 kb
Host smart-8e8eb325-f95d-4c30-932a-0069d55a3ce1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762013837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3762013837
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1924394279
Short name T122
Test name
Test status
Simulation time 9270582824 ps
CPU time 72.75 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:33:40 PM PDT 24
Peak memory 219692 kb
Host smart-919f32bc-0eb6-4d86-b3b6-ee8ad3469554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924394279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1924394279
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.287404647
Short name T58
Test name
Test status
Simulation time 101504425 ps
CPU time 5.97 seconds
Started Jun 22 04:44:41 PM PDT 24
Finished Jun 22 04:44:48 PM PDT 24
Peak memory 211296 kb
Host smart-5e1cb50c-b4ea-4641-bcfb-adbf9e16aeff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287404647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.287404647
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2670172298
Short name T71
Test name
Test status
Simulation time 2447827939 ps
CPU time 8.05 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:47 PM PDT 24
Peak memory 219536 kb
Host smart-ff08e103-ae28-4871-a4c3-ed75fd98988c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670172298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2670172298
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1958194474
Short name T64
Test name
Test status
Simulation time 348156630 ps
CPU time 4.22 seconds
Started Jun 22 04:32:10 PM PDT 24
Finished Jun 22 04:32:14 PM PDT 24
Peak memory 218180 kb
Host smart-c8c4e671-3816-4f73-8883-65dce9fa1d2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958194474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1958194474
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1950707646
Short name T463
Test name
Test status
Simulation time 86640184 ps
CPU time 4.38 seconds
Started Jun 22 04:32:10 PM PDT 24
Finished Jun 22 04:32:16 PM PDT 24
Peak memory 211276 kb
Host smart-719f0cbf-b973-4694-81d3-3dd575d68e8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950707646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1950707646
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3124028789
Short name T441
Test name
Test status
Simulation time 341405790 ps
CPU time 5.82 seconds
Started Jun 22 04:32:10 PM PDT 24
Finished Jun 22 04:32:16 PM PDT 24
Peak memory 219204 kb
Host smart-05eaf03c-bb8c-489d-ba16-d09cab0075d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124028789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3124028789
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1710530988
Short name T410
Test name
Test status
Simulation time 307343071 ps
CPU time 6.63 seconds
Started Jun 22 04:32:14 PM PDT 24
Finished Jun 22 04:32:21 PM PDT 24
Peak memory 219464 kb
Host smart-88521a47-2426-4a48-a494-c7b09781bd1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710530988 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1710530988
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2513790479
Short name T458
Test name
Test status
Simulation time 2751795582 ps
CPU time 13.44 seconds
Started Jun 22 04:32:14 PM PDT 24
Finished Jun 22 04:32:28 PM PDT 24
Peak memory 219544 kb
Host smart-bc45e586-52b2-4e3d-ae81-d51b84ebed0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513790479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2513790479
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.189825337
Short name T421
Test name
Test status
Simulation time 6107412849 ps
CPU time 12.2 seconds
Started Jun 22 04:32:10 PM PDT 24
Finished Jun 22 04:32:23 PM PDT 24
Peak memory 211200 kb
Host smart-34d7b02e-62ba-4b56-b896-be914b5d1d3a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189825337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.189825337
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2757591021
Short name T389
Test name
Test status
Simulation time 4434628321 ps
CPU time 10.47 seconds
Started Jun 22 04:32:12 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 211196 kb
Host smart-63186702-1bd6-4360-beda-36f89a818e8e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757591021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2757591021
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.269213318
Short name T97
Test name
Test status
Simulation time 565966784 ps
CPU time 28.15 seconds
Started Jun 22 04:32:11 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 211664 kb
Host smart-bdbd1619-780d-42b8-bb95-6fa889ae4fc4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269213318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.269213318
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1605284042
Short name T417
Test name
Test status
Simulation time 1755294880 ps
CPU time 14.83 seconds
Started Jun 22 04:32:12 PM PDT 24
Finished Jun 22 04:32:28 PM PDT 24
Peak memory 211304 kb
Host smart-e903e6be-ed9c-458c-b615-994afe0a6944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605284042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1605284042
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4274492759
Short name T422
Test name
Test status
Simulation time 1032812484 ps
CPU time 12.89 seconds
Started Jun 22 04:32:11 PM PDT 24
Finished Jun 22 04:32:25 PM PDT 24
Peak memory 219688 kb
Host smart-406242a5-bb67-4a44-adee-6d10cbc0c7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274492759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4274492759
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.112473217
Short name T112
Test name
Test status
Simulation time 1460650584 ps
CPU time 75 seconds
Started Jun 22 04:32:09 PM PDT 24
Finished Jun 22 04:33:25 PM PDT 24
Peak memory 212772 kb
Host smart-e78fce6c-56a2-485a-913c-4592d802e10e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112473217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.112473217
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.393787575
Short name T446
Test name
Test status
Simulation time 174680092 ps
CPU time 4.23 seconds
Started Jun 22 04:32:10 PM PDT 24
Finished Jun 22 04:32:15 PM PDT 24
Peak memory 211240 kb
Host smart-e3686404-a1b5-4899-959a-9ce161afaf8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393787575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.393787575
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2871659972
Short name T433
Test name
Test status
Simulation time 1877147332 ps
CPU time 14.5 seconds
Started Jun 22 04:32:11 PM PDT 24
Finished Jun 22 04:32:26 PM PDT 24
Peak memory 217680 kb
Host smart-882219c5-3d2e-4edb-94df-644ac3a99948
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871659972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2871659972
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4079612167
Short name T74
Test name
Test status
Simulation time 1944757381 ps
CPU time 18.18 seconds
Started Jun 22 04:32:14 PM PDT 24
Finished Jun 22 04:32:33 PM PDT 24
Peak memory 211240 kb
Host smart-6e066c6c-b7a6-4116-87a0-b7c0c2e19be8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079612167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4079612167
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1667243174
Short name T403
Test name
Test status
Simulation time 102524923 ps
CPU time 5.98 seconds
Started Jun 22 04:32:18 PM PDT 24
Finished Jun 22 04:32:25 PM PDT 24
Peak memory 219560 kb
Host smart-7d459a77-db84-4c69-919d-75cad7096c72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667243174 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1667243174
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2878274712
Short name T394
Test name
Test status
Simulation time 467731169 ps
CPU time 7.44 seconds
Started Jun 22 04:32:09 PM PDT 24
Finished Jun 22 04:32:17 PM PDT 24
Peak memory 211308 kb
Host smart-395e52cf-257e-459f-ab8b-69ed77a2e404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878274712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2878274712
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.727137612
Short name T436
Test name
Test status
Simulation time 818549637 ps
CPU time 8 seconds
Started Jun 22 04:32:11 PM PDT 24
Finished Jun 22 04:32:20 PM PDT 24
Peak memory 211208 kb
Host smart-e27fb7cc-5021-4f04-abf3-c41a47ff12d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727137612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.727137612
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2929479912
Short name T393
Test name
Test status
Simulation time 1518439154 ps
CPU time 12.91 seconds
Started Jun 22 04:32:13 PM PDT 24
Finished Jun 22 04:32:27 PM PDT 24
Peak memory 211108 kb
Host smart-42f26c24-5bb9-45a8-bbba-edd40239b2f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929479912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2929479912
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.93151717
Short name T390
Test name
Test status
Simulation time 3231878131 ps
CPU time 18.64 seconds
Started Jun 22 04:32:09 PM PDT 24
Finished Jun 22 04:32:28 PM PDT 24
Peak memory 211448 kb
Host smart-3818b17c-fb0e-4370-b96e-fd699c5039fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93151717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pass
thru_mem_tl_intg_err.93151717
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3800895978
Short name T462
Test name
Test status
Simulation time 3327839730 ps
CPU time 17.61 seconds
Started Jun 22 04:32:11 PM PDT 24
Finished Jun 22 04:32:30 PM PDT 24
Peak memory 219812 kb
Host smart-c1eebd51-3a62-48f9-a82b-c52f39f8665c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800895978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3800895978
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.26162801
Short name T450
Test name
Test status
Simulation time 18374237489 ps
CPU time 43.21 seconds
Started Jun 22 04:32:13 PM PDT 24
Finished Jun 22 04:32:57 PM PDT 24
Peak memory 219600 kb
Host smart-44b05828-803d-4ff0-8ea8-177d19b8ec9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26162801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg
_err.26162801
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.618609122
Short name T385
Test name
Test status
Simulation time 4129232132 ps
CPU time 8.92 seconds
Started Jun 22 04:32:25 PM PDT 24
Finished Jun 22 04:32:35 PM PDT 24
Peak memory 219608 kb
Host smart-377807de-289e-4616-a333-3367cdaf87c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618609122 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.618609122
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2181311937
Short name T387
Test name
Test status
Simulation time 775217567 ps
CPU time 9.08 seconds
Started Jun 22 04:32:32 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 211240 kb
Host smart-af51cf89-0dbb-441f-800f-b863943ae401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181311937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2181311937
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2716314899
Short name T102
Test name
Test status
Simulation time 26463830376 ps
CPU time 34.72 seconds
Started Jun 22 04:32:25 PM PDT 24
Finished Jun 22 04:33:00 PM PDT 24
Peak memory 211384 kb
Host smart-b475b2a4-8e0f-4f51-a7a5-05eaf26eb1c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716314899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2716314899
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.23238482
Short name T104
Test name
Test status
Simulation time 2302876028 ps
CPU time 12.6 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 219564 kb
Host smart-0a126451-b9a5-4678-ada6-8d8f0bbd1b90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23238482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ct
rl_same_csr_outstanding.23238482
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.977368329
Short name T426
Test name
Test status
Simulation time 3585265685 ps
CPU time 18.06 seconds
Started Jun 22 04:32:31 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 219536 kb
Host smart-7b2fa644-16ca-40b9-93c1-92e9903e548d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977368329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.977368329
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4253309900
Short name T457
Test name
Test status
Simulation time 1346848254 ps
CPU time 43.66 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 212344 kb
Host smart-78a71528-828d-4d75-9237-219e611c40c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253309900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4253309900
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.215093532
Short name T400
Test name
Test status
Simulation time 1449186103 ps
CPU time 12.86 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:32:44 PM PDT 24
Peak memory 219508 kb
Host smart-45bc3a6b-b155-4ff2-ba32-7fd996742a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215093532 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.215093532
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.922664809
Short name T398
Test name
Test status
Simulation time 292906852 ps
CPU time 6.12 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:35 PM PDT 24
Peak memory 211216 kb
Host smart-dc065240-d92f-4971-a4ff-4141a579e21a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922664809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.922664809
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2236444253
Short name T423
Test name
Test status
Simulation time 20131793167 ps
CPU time 50.41 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 211428 kb
Host smart-ec826296-7598-4f8d-abd6-04622389e75e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236444253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2236444253
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1181145604
Short name T105
Test name
Test status
Simulation time 2160033179 ps
CPU time 9.87 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 211424 kb
Host smart-da7720ac-aab5-412c-a2f4-e758c8aa0df8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181145604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1181145604
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1194620138
Short name T466
Test name
Test status
Simulation time 7810423224 ps
CPU time 16.14 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 219540 kb
Host smart-7c3f9bdd-b24f-4e4e-bffc-4dd4f57059aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194620138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1194620138
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3671734252
Short name T116
Test name
Test status
Simulation time 4458474689 ps
CPU time 47.6 seconds
Started Jun 22 04:32:25 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 219692 kb
Host smart-542cbe4f-893c-4734-843d-62dc42675b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671734252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3671734252
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2380758336
Short name T424
Test name
Test status
Simulation time 381240656 ps
CPU time 4.3 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:32:33 PM PDT 24
Peak memory 213304 kb
Host smart-2daae130-1df0-4244-8e86-95db0c7daa39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380758336 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2380758336
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3770936714
Short name T425
Test name
Test status
Simulation time 1931443822 ps
CPU time 15.65 seconds
Started Jun 22 04:32:29 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 219292 kb
Host smart-efb52850-b35b-4700-bfd3-38bf01748793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770936714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3770936714
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1863819616
Short name T76
Test name
Test status
Simulation time 6964813835 ps
CPU time 29.82 seconds
Started Jun 22 04:32:32 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 211228 kb
Host smart-fc5b2b8c-9024-4833-8b55-d0b0ea5593bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863819616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1863819616
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4032423715
Short name T396
Test name
Test status
Simulation time 1107451192 ps
CPU time 10.67 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 219512 kb
Host smart-6d6bbc82-5fef-4577-9774-c4064847cd97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032423715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4032423715
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1485796330
Short name T388
Test name
Test status
Simulation time 361617723 ps
CPU time 8.31 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 216264 kb
Host smart-35863b94-7810-4fe6-b2f6-e904a0ca6e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485796330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1485796330
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1912112444
Short name T397
Test name
Test status
Simulation time 459918469 ps
CPU time 5.23 seconds
Started Jun 22 04:32:32 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 219524 kb
Host smart-cf10065f-a1ad-4ad3-9028-abeef9bafd9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912112444 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1912112444
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3299626173
Short name T430
Test name
Test status
Simulation time 592510705 ps
CPU time 7.63 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 211240 kb
Host smart-1a51b123-4b88-48bd-9864-fe2dd041d9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299626173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3299626173
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2470404252
Short name T406
Test name
Test status
Simulation time 2361425095 ps
CPU time 26.03 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:32:57 PM PDT 24
Peak memory 211416 kb
Host smart-f3f7681f-dd64-4384-bfac-e9c985747485
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470404252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2470404252
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2936672416
Short name T447
Test name
Test status
Simulation time 5547794018 ps
CPU time 12.32 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 211428 kb
Host smart-2f77b1d9-3dfa-41da-87b2-66d9560c223a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936672416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2936672416
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1504761434
Short name T439
Test name
Test status
Simulation time 1151483599 ps
CPU time 9.81 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 219416 kb
Host smart-b0c80176-4cc5-4668-8699-d15381ceb1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504761434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1504761434
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.774792930
Short name T117
Test name
Test status
Simulation time 238605621 ps
CPU time 68.95 seconds
Started Jun 22 04:32:26 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 212908 kb
Host smart-091c1b31-ba40-4090-ab0c-7ea009d14c50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774792930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.774792930
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2536853281
Short name T383
Test name
Test status
Simulation time 10463320169 ps
CPU time 14.29 seconds
Started Jun 22 04:32:29 PM PDT 24
Finished Jun 22 04:32:44 PM PDT 24
Peak memory 219560 kb
Host smart-8e0be9ea-b236-46c8-bcab-edc0cfd1081a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536853281 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2536853281
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.678913525
Short name T414
Test name
Test status
Simulation time 1906801496 ps
CPU time 7.5 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 217980 kb
Host smart-613a5db5-131d-4830-ba85-99757646b170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678913525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.678913525
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2401776719
Short name T91
Test name
Test status
Simulation time 10976147576 ps
CPU time 48.25 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 211428 kb
Host smart-62bff137-7a49-4ccc-a74e-84d350ad203c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401776719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2401776719
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3414065560
Short name T415
Test name
Test status
Simulation time 2069247154 ps
CPU time 11.62 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 211404 kb
Host smart-15d73b11-4d5a-4da8-89b3-138ea5009473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414065560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3414065560
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3235674708
Short name T468
Test name
Test status
Simulation time 166105214 ps
CPU time 9.53 seconds
Started Jun 22 04:32:29 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 219332 kb
Host smart-9e68774c-bcfe-4094-a9a9-ffdaa9db36c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235674708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3235674708
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2338571982
Short name T113
Test name
Test status
Simulation time 651212382 ps
CPU time 70.05 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:33:41 PM PDT 24
Peak memory 219448 kb
Host smart-4f469e04-c872-432f-8b80-b35a92f56e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338571982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2338571982
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2056164619
Short name T412
Test name
Test status
Simulation time 18653304746 ps
CPU time 14.79 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 219584 kb
Host smart-26b7d2fa-070d-4f2d-9531-7c7aa0f3a484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056164619 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2056164619
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.259851946
Short name T384
Test name
Test status
Simulation time 1645734924 ps
CPU time 9.75 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 211244 kb
Host smart-15ba8a27-3ee2-4bf9-97f4-bf5089006ec8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259851946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.259851946
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1434226037
Short name T435
Test name
Test status
Simulation time 11502274781 ps
CPU time 59.6 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 211416 kb
Host smart-49a92025-88e7-415a-a38f-d8fc8cbb8926
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434226037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1434226037
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.5474219
Short name T73
Test name
Test status
Simulation time 1545233315 ps
CPU time 12.73 seconds
Started Jun 22 04:32:32 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 219288 kb
Host smart-5e586cfb-2a8b-4b1f-8046-58d0dbed5a61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5474219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctr
l_same_csr_outstanding.5474219
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3861135823
Short name T452
Test name
Test status
Simulation time 626659059 ps
CPU time 9.51 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 219492 kb
Host smart-cb25c0d1-1ada-4386-9f8c-afe9b8713836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861135823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3861135823
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.857088851
Short name T119
Test name
Test status
Simulation time 1507614878 ps
CPU time 35.6 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:33:04 PM PDT 24
Peak memory 219448 kb
Host smart-9fa8a911-c74c-49e5-8df3-5cf87ae84ec9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857088851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.857088851
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3827403321
Short name T465
Test name
Test status
Simulation time 1537856473 ps
CPU time 12.92 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:48 PM PDT 24
Peak memory 215136 kb
Host smart-a0b7e553-c259-467c-8536-4b98f8fc8aef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827403321 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3827403321
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.149726903
Short name T107
Test name
Test status
Simulation time 191108685 ps
CPU time 4.29 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 211244 kb
Host smart-ec965276-14ed-4dcc-9f22-c42d1c4d9cd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149726903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.149726903
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.507844182
Short name T90
Test name
Test status
Simulation time 34915904038 ps
CPU time 62.75 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:33:37 PM PDT 24
Peak memory 211388 kb
Host smart-68d452dd-aaab-4e0e-9ab1-7ef813adb66c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507844182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.507844182
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.250033902
Short name T453
Test name
Test status
Simulation time 3087579058 ps
CPU time 12.81 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 211424 kb
Host smart-335f3375-739b-4cb1-a360-e26f6f70d508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250033902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.250033902
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3424528153
Short name T416
Test name
Test status
Simulation time 1308136083 ps
CPU time 15.06 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 217120 kb
Host smart-1881d5eb-c6dc-45b9-a705-bc9ac5df2866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424528153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3424528153
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2055856761
Short name T434
Test name
Test status
Simulation time 3335566033 ps
CPU time 76.99 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 219568 kb
Host smart-c90c8d81-11bf-4621-95ed-2029811bfa57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055856761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2055856761
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3665359749
Short name T413
Test name
Test status
Simulation time 227156842 ps
CPU time 5.14 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 219468 kb
Host smart-f1ea861a-0bc3-4968-b405-10c7febab860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665359749 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3665359749
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3381526072
Short name T381
Test name
Test status
Simulation time 1264996705 ps
CPU time 11.36 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 219092 kb
Host smart-205aca65-4760-4ab6-b24f-ffc8eb0e600d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381526072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3381526072
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3453508389
Short name T75
Test name
Test status
Simulation time 30521209937 ps
CPU time 95.18 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:34:14 PM PDT 24
Peak memory 211544 kb
Host smart-cbb57df0-6026-44da-b100-03faf71e54b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453508389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3453508389
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1148214206
Short name T103
Test name
Test status
Simulation time 217231038 ps
CPU time 7.5 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:47 PM PDT 24
Peak memory 211312 kb
Host smart-4ba44dca-77d9-4e36-8596-e9e34d5e0880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148214206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1148214206
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2122542071
Short name T401
Test name
Test status
Simulation time 3226120464 ps
CPU time 15.33 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 219536 kb
Host smart-562145ef-1c19-4068-9721-209c00602b75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122542071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2122542071
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1462409631
Short name T444
Test name
Test status
Simulation time 238138855 ps
CPU time 68.53 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:33:45 PM PDT 24
Peak memory 219448 kb
Host smart-5458292c-a188-4aca-8c2a-4f6a1e6351a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462409631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1462409631
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4157743566
Short name T399
Test name
Test status
Simulation time 201560320 ps
CPU time 4.98 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 219448 kb
Host smart-ccba6846-fb3e-432e-8bf4-2e5f5923bf55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157743566 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4157743566
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1109963951
Short name T92
Test name
Test status
Simulation time 1213327151 ps
CPU time 6 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 218132 kb
Host smart-703d005b-1b95-45fd-a307-893d71f60cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109963951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1109963951
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1307797558
Short name T101
Test name
Test status
Simulation time 174884425 ps
CPU time 5.92 seconds
Started Jun 22 04:32:31 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 219432 kb
Host smart-5466664e-ff45-41f6-bba3-a5a4a6e00df5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307797558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1307797558
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3970561840
Short name T376
Test name
Test status
Simulation time 4870100760 ps
CPU time 14.05 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:54 PM PDT 24
Peak memory 219628 kb
Host smart-3888fadb-fd98-4453-9821-ce3760dfcebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970561840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3970561840
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2876711851
Short name T118
Test name
Test status
Simulation time 772689563 ps
CPU time 39.62 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 219448 kb
Host smart-80657c8f-5b74-43fa-b98c-ca77f7e1c68d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876711851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2876711851
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3234751726
Short name T445
Test name
Test status
Simulation time 7888663025 ps
CPU time 15.48 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 219588 kb
Host smart-a52a92a2-049f-4c6f-a144-700526927a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234751726 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3234751726
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1758951994
Short name T408
Test name
Test status
Simulation time 2777672919 ps
CPU time 8.59 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 218240 kb
Host smart-ace7fe86-4ba0-444a-807e-65ad2da1ea9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758951994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1758951994
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3386134014
Short name T78
Test name
Test status
Simulation time 546210098 ps
CPU time 27.55 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:33:03 PM PDT 24
Peak memory 211328 kb
Host smart-de410107-f98a-44d5-b601-529d0dda8a6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386134014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3386134014
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1958004326
Short name T72
Test name
Test status
Simulation time 20534985146 ps
CPU time 15.18 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:55 PM PDT 24
Peak memory 211808 kb
Host smart-0cc9a225-5be8-4ab1-97b3-fcd9f06e07fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958004326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1958004326
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2714928652
Short name T442
Test name
Test status
Simulation time 5207930804 ps
CPU time 13.47 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 219540 kb
Host smart-5c2958cd-b306-4fad-80a8-613bfb0c1f86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714928652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2714928652
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.434157574
Short name T63
Test name
Test status
Simulation time 242357183 ps
CPU time 38.19 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 212756 kb
Host smart-1dea7027-a543-4657-be44-a18d869e216a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434157574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.434157574
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.635576268
Short name T93
Test name
Test status
Simulation time 5590346078 ps
CPU time 10.62 seconds
Started Jun 22 04:32:21 PM PDT 24
Finished Jun 22 04:32:32 PM PDT 24
Peak memory 219564 kb
Host smart-7da7f48d-c8ec-473c-9282-91d9252d7936
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635576268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.635576268
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1415284312
Short name T460
Test name
Test status
Simulation time 1664824713 ps
CPU time 14.21 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:34 PM PDT 24
Peak memory 210968 kb
Host smart-ad249806-9ac6-441a-b239-d919318aafb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415284312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1415284312
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.558895806
Short name T89
Test name
Test status
Simulation time 8567996834 ps
CPU time 17.92 seconds
Started Jun 22 04:32:18 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 219660 kb
Host smart-785b051d-03bd-4582-a1fd-72ad2860ad0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558895806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.558895806
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3782847669
Short name T382
Test name
Test status
Simulation time 5378553370 ps
CPU time 12.92 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:33 PM PDT 24
Peak memory 219212 kb
Host smart-aff543d8-47a4-4a12-b917-4eb3f4b27549
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782847669 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3782847669
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1675290783
Short name T88
Test name
Test status
Simulation time 811110846 ps
CPU time 9.08 seconds
Started Jun 22 04:32:20 PM PDT 24
Finished Jun 22 04:32:30 PM PDT 24
Peak memory 211212 kb
Host smart-8b5f1f83-3c67-4734-a5a3-a51e270431fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675290783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1675290783
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1272584707
Short name T380
Test name
Test status
Simulation time 3960788598 ps
CPU time 10.24 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:29 PM PDT 24
Peak memory 211184 kb
Host smart-605e339b-3f37-4555-8d7b-0493e5969d59
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272584707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1272584707
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.324165735
Short name T407
Test name
Test status
Simulation time 8938748419 ps
CPU time 16.69 seconds
Started Jun 22 04:32:20 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 211196 kb
Host smart-435d2229-15dc-4f5f-8385-8d41752efd57
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324165735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
324165735
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1776983209
Short name T95
Test name
Test status
Simulation time 3264052496 ps
CPU time 36.9 seconds
Started Jun 22 04:32:18 PM PDT 24
Finished Jun 22 04:32:55 PM PDT 24
Peak memory 211420 kb
Host smart-9cf1ba7d-1c3e-4698-b611-ad2b1325b546
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776983209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1776983209
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1018232313
Short name T467
Test name
Test status
Simulation time 663231793 ps
CPU time 9.9 seconds
Started Jun 22 04:32:21 PM PDT 24
Finished Jun 22 04:32:31 PM PDT 24
Peak memory 211644 kb
Host smart-2189a684-2282-4ee2-83e5-faec1916f0ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018232313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1018232313
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3256735679
Short name T469
Test name
Test status
Simulation time 334557257 ps
CPU time 9.52 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:29 PM PDT 24
Peak memory 219412 kb
Host smart-72e47907-f95c-47bb-9b1f-891d1a238138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256735679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3256735679
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1044432371
Short name T379
Test name
Test status
Simulation time 7937626780 ps
CPU time 12.92 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:33 PM PDT 24
Peak memory 219556 kb
Host smart-ed1ce526-4849-4c30-9271-fa713104a265
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044432371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1044432371
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2751401111
Short name T448
Test name
Test status
Simulation time 90167781 ps
CPU time 5.83 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:26 PM PDT 24
Peak memory 211308 kb
Host smart-3cfe825e-746c-490c-879f-06b98c942215
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751401111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2751401111
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4079286309
Short name T378
Test name
Test status
Simulation time 6245928280 ps
CPU time 12.3 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:33 PM PDT 24
Peak memory 219636 kb
Host smart-f4b15315-6629-4e6f-8ee5-0d5fd3115f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079286309 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4079286309
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.540344375
Short name T79
Test name
Test status
Simulation time 2109457934 ps
CPU time 10.45 seconds
Started Jun 22 04:32:20 PM PDT 24
Finished Jun 22 04:32:31 PM PDT 24
Peak memory 211216 kb
Host smart-6a76b71f-be07-44ef-baaf-193400c74c60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540344375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.540344375
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.150277401
Short name T409
Test name
Test status
Simulation time 182278780 ps
CPU time 4.15 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 211112 kb
Host smart-2b30913e-86e6-4e56-94bc-44132bfee241
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150277401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.150277401
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.27080055
Short name T402
Test name
Test status
Simulation time 5204473758 ps
CPU time 15.68 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:35 PM PDT 24
Peak memory 211296 kb
Host smart-2fda2161-230f-4e84-ba05-1cb4de5c3881
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.27080055
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3970611945
Short name T96
Test name
Test status
Simulation time 2830037893 ps
CPU time 36.1 seconds
Started Jun 22 04:32:21 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 211784 kb
Host smart-9ebff557-2c3f-4581-9d56-5e73c7784555
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970611945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3970611945
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2913896854
Short name T470
Test name
Test status
Simulation time 3657733790 ps
CPU time 15.2 seconds
Started Jun 22 04:32:20 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 219552 kb
Host smart-d067f861-3446-4de5-b710-2edc6297f658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913896854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2913896854
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3132777700
Short name T375
Test name
Test status
Simulation time 4350346786 ps
CPU time 17.73 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 219448 kb
Host smart-17e04d44-ed1e-4974-b561-a085085b9d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132777700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3132777700
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3987117497
Short name T115
Test name
Test status
Simulation time 627403153 ps
CPU time 72.64 seconds
Started Jun 22 04:32:20 PM PDT 24
Finished Jun 22 04:33:34 PM PDT 24
Peak memory 211516 kb
Host smart-afc7c270-7be8-4945-9155-ba472bcaa7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987117497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3987117497
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3616045944
Short name T428
Test name
Test status
Simulation time 1325226845 ps
CPU time 11.99 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:32 PM PDT 24
Peak memory 211304 kb
Host smart-206f99f1-f4b1-4628-8687-bb1e19be99cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616045944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3616045944
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2690354648
Short name T455
Test name
Test status
Simulation time 6246525818 ps
CPU time 14.22 seconds
Started Jun 22 04:32:23 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 218804 kb
Host smart-427f95fb-9af2-4e9c-95b7-8ce1ada06dcb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690354648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2690354648
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2699697673
Short name T391
Test name
Test status
Simulation time 3555903517 ps
CPU time 10.85 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:30 PM PDT 24
Peak memory 218184 kb
Host smart-72f1ba27-9df0-454d-94cc-f48e5099e068
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699697673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2699697673
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1788303013
Short name T432
Test name
Test status
Simulation time 6046849775 ps
CPU time 8.7 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:28 PM PDT 24
Peak memory 219580 kb
Host smart-4f0a0bb8-e7ab-4e3b-bf95-75789c121869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788303013 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1788303013
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1664485567
Short name T449
Test name
Test status
Simulation time 2141126015 ps
CPU time 10.56 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:31 PM PDT 24
Peak memory 211304 kb
Host smart-0924b5ca-d1b2-488d-a460-f08a03cb3d50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664485567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1664485567
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2823951536
Short name T459
Test name
Test status
Simulation time 2083495194 ps
CPU time 15.47 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:35 PM PDT 24
Peak memory 211112 kb
Host smart-b933ae9c-9b9a-46db-8f47-348cbe269d13
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823951536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2823951536
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1037989730
Short name T431
Test name
Test status
Simulation time 730992489 ps
CPU time 8.53 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:29 PM PDT 24
Peak memory 211076 kb
Host smart-fcdc37f7-d954-4364-9432-5ce58ea00634
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037989730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1037989730
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1133894942
Short name T461
Test name
Test status
Simulation time 46997174376 ps
CPU time 83.28 seconds
Started Jun 22 04:32:23 PM PDT 24
Finished Jun 22 04:33:46 PM PDT 24
Peak memory 211432 kb
Host smart-05a5da5f-bb5c-4b22-bc63-f1db97882a48
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133894942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1133894942
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1021986908
Short name T427
Test name
Test status
Simulation time 2040435112 ps
CPU time 17.67 seconds
Started Jun 22 04:32:16 PM PDT 24
Finished Jun 22 04:32:34 PM PDT 24
Peak memory 219440 kb
Host smart-252c493b-1222-46a8-9d8c-84d2bb2b735f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021986908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1021986908
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1946236156
Short name T404
Test name
Test status
Simulation time 1150441891 ps
CPU time 12.09 seconds
Started Jun 22 04:32:19 PM PDT 24
Finished Jun 22 04:32:32 PM PDT 24
Peak memory 219416 kb
Host smart-ee154b10-199b-421f-8118-b31d33d7892e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946236156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1946236156
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3495975383
Short name T114
Test name
Test status
Simulation time 584882251 ps
CPU time 68.92 seconds
Started Jun 22 04:32:20 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 219788 kb
Host smart-51c386a1-6283-4492-9816-272d29ec26ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495975383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3495975383
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1565682143
Short name T419
Test name
Test status
Simulation time 93691378 ps
CPU time 4.61 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:32:34 PM PDT 24
Peak memory 219528 kb
Host smart-38d65001-77ab-4a7b-9152-69d3dcc21c0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565682143 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1565682143
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.734258840
Short name T98
Test name
Test status
Simulation time 1036826047 ps
CPU time 6.07 seconds
Started Jun 22 04:32:18 PM PDT 24
Finished Jun 22 04:32:25 PM PDT 24
Peak memory 211244 kb
Host smart-54bdc2a7-669e-4af9-a2e8-417f0f3942f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734258840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.734258840
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.451627702
Short name T65
Test name
Test status
Simulation time 9403000687 ps
CPU time 68.84 seconds
Started Jun 22 04:32:21 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 211504 kb
Host smart-b3fc2bb6-9385-46ad-83a2-38fbf3a39c5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451627702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.451627702
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2084276287
Short name T440
Test name
Test status
Simulation time 4959867265 ps
CPU time 5.87 seconds
Started Jun 22 04:32:18 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 211420 kb
Host smart-51c15925-9460-452b-9863-ed0e0904b6d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084276287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2084276287
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3528302315
Short name T405
Test name
Test status
Simulation time 3040114147 ps
CPU time 14.23 seconds
Started Jun 22 04:32:21 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 219512 kb
Host smart-7f83a890-7bba-4e7d-b67f-2eeca8ba2877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528302315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3528302315
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.325279637
Short name T61
Test name
Test status
Simulation time 684120307 ps
CPU time 36.25 seconds
Started Jun 22 04:32:16 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 219476 kb
Host smart-5f9320e5-1580-4191-bab3-efd9e3ace177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325279637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.325279637
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1090146870
Short name T456
Test name
Test status
Simulation time 1829549085 ps
CPU time 14.61 seconds
Started Jun 22 04:32:26 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 219528 kb
Host smart-27d9b824-3755-4970-9adb-d369db6207bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090146870 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1090146870
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.775027842
Short name T106
Test name
Test status
Simulation time 90102185 ps
CPU time 4.22 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:32 PM PDT 24
Peak memory 211304 kb
Host smart-a991f485-50be-458e-94db-6d381eeb292a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775027842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.775027842
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.243855672
Short name T395
Test name
Test status
Simulation time 13029138296 ps
CPU time 46.38 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 211392 kb
Host smart-c72783f4-ad16-4039-8447-87c1c58f8fae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243855672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.243855672
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2161013503
Short name T100
Test name
Test status
Simulation time 1461357606 ps
CPU time 14.28 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 212188 kb
Host smart-57eb2a3a-2e9b-4ada-a02d-ecd0740943ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161013503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2161013503
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.305879847
Short name T464
Test name
Test status
Simulation time 1195652419 ps
CPU time 11.47 seconds
Started Jun 22 04:32:25 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 219512 kb
Host smart-ef254c10-c1eb-4b5c-9d3d-f87d6fd79026
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305879847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.305879847
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4171932742
Short name T418
Test name
Test status
Simulation time 8977289044 ps
CPU time 78.96 seconds
Started Jun 22 04:32:25 PM PDT 24
Finished Jun 22 04:33:45 PM PDT 24
Peak memory 219940 kb
Host smart-c90fe27f-386f-4a98-91b2-128094d93e31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171932742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4171932742
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.881977977
Short name T411
Test name
Test status
Simulation time 949090913 ps
CPU time 10 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 219496 kb
Host smart-43878ff2-90e9-450f-b0fd-672f392e2cb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881977977 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.881977977
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4039099497
Short name T451
Test name
Test status
Simulation time 169832971 ps
CPU time 5.4 seconds
Started Jun 22 04:32:26 PM PDT 24
Finished Jun 22 04:32:32 PM PDT 24
Peak memory 211276 kb
Host smart-ca4cbb39-f685-46df-a698-78b81391b71b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039099497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4039099497
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4142063678
Short name T392
Test name
Test status
Simulation time 108658305644 ps
CPU time 94.68 seconds
Started Jun 22 04:32:26 PM PDT 24
Finished Jun 22 04:34:01 PM PDT 24
Peak memory 211452 kb
Host smart-9b24bfaa-277d-4023-94fa-4fcba030a4cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142063678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4142063678
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2913658150
Short name T438
Test name
Test status
Simulation time 1157772293 ps
CPU time 11.06 seconds
Started Jun 22 04:32:25 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 219488 kb
Host smart-1b5a0934-a6ad-4eec-9b2f-db97b774b9b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913658150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2913658150
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4261221581
Short name T429
Test name
Test status
Simulation time 1392899245 ps
CPU time 15.91 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:32:46 PM PDT 24
Peak memory 219416 kb
Host smart-347c59fc-e205-45c4-9c7f-635e11ecef3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261221581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4261221581
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1334702241
Short name T121
Test name
Test status
Simulation time 6258866730 ps
CPU time 73.91 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:33:43 PM PDT 24
Peak memory 213088 kb
Host smart-21cafe69-9241-456c-9f8a-d1589352845d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334702241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1334702241
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2370842297
Short name T420
Test name
Test status
Simulation time 2204098567 ps
CPU time 9.21 seconds
Started Jun 22 04:32:26 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 219580 kb
Host smart-5e225daa-709c-4df7-8978-bc27116abb3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370842297 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2370842297
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2955695422
Short name T454
Test name
Test status
Simulation time 3005413712 ps
CPU time 9.05 seconds
Started Jun 22 04:32:26 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 211432 kb
Host smart-f289eadd-006b-47c2-9e98-be9acfdca11f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955695422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2955695422
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2897315421
Short name T94
Test name
Test status
Simulation time 27767809187 ps
CPU time 59.18 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 211452 kb
Host smart-3ce7025d-d664-445d-b7ed-a54107e08ae0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897315421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2897315421
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.440907486
Short name T77
Test name
Test status
Simulation time 506431787 ps
CPU time 7.42 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 218588 kb
Host smart-61afbc4b-9654-4224-89c7-5dc01dcb7d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440907486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.440907486
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.209216957
Short name T443
Test name
Test status
Simulation time 190994898 ps
CPU time 6.62 seconds
Started Jun 22 04:32:30 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 219396 kb
Host smart-46d84fcf-bd9d-464e-aa66-5f2d9a349389
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209216957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.209216957
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.400338222
Short name T377
Test name
Test status
Simulation time 25875600346 ps
CPU time 12.12 seconds
Started Jun 22 04:32:27 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 219644 kb
Host smart-43d52f1e-bb66-473d-90ce-edb56a058b9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400338222 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.400338222
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.451356206
Short name T108
Test name
Test status
Simulation time 3507850822 ps
CPU time 10.2 seconds
Started Jun 22 04:32:29 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 211360 kb
Host smart-c7c96362-4470-45f6-8674-448b11846db4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451356206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.451356206
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3576379570
Short name T87
Test name
Test status
Simulation time 50442777534 ps
CPU time 94.71 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:34:04 PM PDT 24
Peak memory 211452 kb
Host smart-c258636f-c33b-4838-bbb1-b515da5eb9ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576379570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3576379570
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3271522901
Short name T437
Test name
Test status
Simulation time 1889917924 ps
CPU time 17.33 seconds
Started Jun 22 04:33:43 PM PDT 24
Finished Jun 22 04:34:02 PM PDT 24
Peak memory 211288 kb
Host smart-74ec1a77-42b0-4de9-b3d5-3d064939d89f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271522901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3271522901
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2886436478
Short name T386
Test name
Test status
Simulation time 1857499603 ps
CPU time 17.37 seconds
Started Jun 22 04:32:31 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 219420 kb
Host smart-b86a55bf-7376-4556-9d5c-72da452dda45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886436478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2886436478
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1167033349
Short name T123
Test name
Test status
Simulation time 246613822 ps
CPU time 68.94 seconds
Started Jun 22 04:32:28 PM PDT 24
Finished Jun 22 04:33:38 PM PDT 24
Peak memory 211880 kb
Host smart-86615a77-f73c-457d-8b67-a4b5eb306ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167033349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1167033349
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2371838065
Short name T265
Test name
Test status
Simulation time 12862616708 ps
CPU time 108.59 seconds
Started Jun 22 04:44:42 PM PDT 24
Finished Jun 22 04:46:31 PM PDT 24
Peak memory 228448 kb
Host smart-b02b87ce-3741-4c9e-9fde-36af1b2b2707
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371838065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2371838065
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.872741496
Short name T357
Test name
Test status
Simulation time 1226930138 ps
CPU time 17.88 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:44:59 PM PDT 24
Peak memory 211856 kb
Host smart-823c3a50-00c1-47cc-ab03-d318cfb686ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872741496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.872741496
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.757768778
Short name T236
Test name
Test status
Simulation time 207164857 ps
CPU time 5.63 seconds
Started Jun 22 04:44:39 PM PDT 24
Finished Jun 22 04:44:46 PM PDT 24
Peak memory 211252 kb
Host smart-db90ed46-51fb-41a9-add9-9fc8e59c7b69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757768778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.757768778
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.702345732
Short name T19
Test name
Test status
Simulation time 1983649885 ps
CPU time 108.43 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:46:57 PM PDT 24
Peak memory 235436 kb
Host smart-f8d0580f-38b0-41b1-87e1-ed0b05879f4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702345732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.702345732
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2165654242
Short name T358
Test name
Test status
Simulation time 683504017 ps
CPU time 14.66 seconds
Started Jun 22 04:44:41 PM PDT 24
Finished Jun 22 04:44:56 PM PDT 24
Peak memory 213404 kb
Host smart-bf18791b-7d40-44b3-b0eb-3a519ede61e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165654242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2165654242
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.921640439
Short name T251
Test name
Test status
Simulation time 715671185 ps
CPU time 17.47 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:44:58 PM PDT 24
Peak memory 214796 kb
Host smart-df78a15c-aef8-44c0-b250-067bf3acdd13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921640439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.921640439
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3509051188
Short name T21
Test name
Test status
Simulation time 1685187330 ps
CPU time 10.9 seconds
Started Jun 22 04:44:39 PM PDT 24
Finished Jun 22 04:44:50 PM PDT 24
Peak memory 211032 kb
Host smart-f6bbb867-15cd-40b3-8632-d251ad606982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509051188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3509051188
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3589464926
Short name T239
Test name
Test status
Simulation time 61134048619 ps
CPU time 36.1 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:45:17 PM PDT 24
Peak memory 212168 kb
Host smart-bb1a3568-dd2e-4e56-97cb-1cbcad97a8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589464926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3589464926
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1948345175
Short name T211
Test name
Test status
Simulation time 8985806941 ps
CPU time 17.9 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:44:59 PM PDT 24
Peak memory 211168 kb
Host smart-bf7780ba-0950-4db9-956e-e2957458b986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948345175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1948345175
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3103146265
Short name T329
Test name
Test status
Simulation time 4092867609 ps
CPU time 32.37 seconds
Started Jun 22 04:44:42 PM PDT 24
Finished Jun 22 04:45:14 PM PDT 24
Peak memory 213212 kb
Host smart-0b86eff4-8a9d-4712-b180-467577c1f633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103146265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3103146265
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.663348648
Short name T10
Test name
Test status
Simulation time 7702801622 ps
CPU time 68.71 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:45:50 PM PDT 24
Peak memory 219548 kb
Host smart-377c1e94-a497-45f4-8173-de0b9e62a25c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663348648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.663348648
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1644136132
Short name T51
Test name
Test status
Simulation time 107190115287 ps
CPU time 1007.99 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 05:01:29 PM PDT 24
Peak memory 235684 kb
Host smart-58db4879-41f4-41a0-b44d-f487200895ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644136132 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1644136132
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2274055696
Short name T194
Test name
Test status
Simulation time 88923805 ps
CPU time 4.32 seconds
Started Jun 22 04:45:02 PM PDT 24
Finished Jun 22 04:45:06 PM PDT 24
Peak memory 211136 kb
Host smart-f7da3728-e21e-42a2-99f5-a7ea00d905b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274055696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2274055696
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4255963919
Short name T39
Test name
Test status
Simulation time 132917045105 ps
CPU time 333.48 seconds
Started Jun 22 04:44:57 PM PDT 24
Finished Jun 22 04:50:31 PM PDT 24
Peak memory 224316 kb
Host smart-d6691ac0-2f77-4377-8d46-b3bd586ed876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255963919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4255963919
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2758233762
Short name T174
Test name
Test status
Simulation time 4301292688 ps
CPU time 11.64 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:02 PM PDT 24
Peak memory 211324 kb
Host smart-a616cf6e-ba0f-41bd-bd75-3e5f5a768fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758233762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2758233762
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2745135136
Short name T165
Test name
Test status
Simulation time 1427697467 ps
CPU time 21.84 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:13 PM PDT 24
Peak memory 213084 kb
Host smart-41a10b18-9577-4d2e-ad20-9bc788bbdc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745135136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2745135136
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4245414371
Short name T160
Test name
Test status
Simulation time 15279685136 ps
CPU time 47 seconds
Started Jun 22 04:44:54 PM PDT 24
Finished Jun 22 04:45:41 PM PDT 24
Peak memory 214384 kb
Host smart-46ac514d-abde-4900-bf80-b151060be39d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245414371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4245414371
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1608360743
Short name T241
Test name
Test status
Simulation time 28763870597 ps
CPU time 1116.31 seconds
Started Jun 22 04:44:58 PM PDT 24
Finished Jun 22 05:03:35 PM PDT 24
Peak memory 235848 kb
Host smart-452cbe88-f874-4819-b35e-abda925cb08b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608360743 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1608360743
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1498677794
Short name T292
Test name
Test status
Simulation time 1605636824 ps
CPU time 13.51 seconds
Started Jun 22 04:45:20 PM PDT 24
Finished Jun 22 04:45:34 PM PDT 24
Peak memory 211084 kb
Host smart-ca48d2af-cd70-46fc-b513-add06a6e29b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498677794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1498677794
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1384645101
Short name T289
Test name
Test status
Simulation time 2715387838 ps
CPU time 26.25 seconds
Started Jun 22 04:45:00 PM PDT 24
Finished Jun 22 04:45:26 PM PDT 24
Peak memory 211816 kb
Host smart-9d0474b7-ef6f-4abd-b434-f322d44db12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384645101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1384645101
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.287617561
Short name T128
Test name
Test status
Simulation time 3353182814 ps
CPU time 15.01 seconds
Started Jun 22 04:44:57 PM PDT 24
Finished Jun 22 04:45:13 PM PDT 24
Peak memory 211308 kb
Host smart-058d7ebe-1323-4afe-81a6-64f219f4a9c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287617561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.287617561
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2293294578
Short name T363
Test name
Test status
Simulation time 190717410 ps
CPU time 10.18 seconds
Started Jun 22 04:45:02 PM PDT 24
Finished Jun 22 04:45:12 PM PDT 24
Peak memory 213892 kb
Host smart-19f97881-c95a-46f3-a042-28ce4735aec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293294578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2293294578
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.380671724
Short name T362
Test name
Test status
Simulation time 309143790 ps
CPU time 15.61 seconds
Started Jun 22 04:44:56 PM PDT 24
Finished Jun 22 04:45:12 PM PDT 24
Peak memory 213716 kb
Host smart-bde8014f-d440-4fd1-9306-372d02bc98b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380671724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.380671724
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2000743530
Short name T144
Test name
Test status
Simulation time 9398890015 ps
CPU time 15.45 seconds
Started Jun 22 04:45:00 PM PDT 24
Finished Jun 22 04:45:16 PM PDT 24
Peak memory 211204 kb
Host smart-7ffd7745-5232-425d-b430-de9f6e111d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000743530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2000743530
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.192015624
Short name T320
Test name
Test status
Simulation time 32023449480 ps
CPU time 122.46 seconds
Started Jun 22 04:45:00 PM PDT 24
Finished Jun 22 04:47:03 PM PDT 24
Peak memory 236548 kb
Host smart-deee4c63-0910-451c-b507-38bb5cfa25c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192015624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.192015624
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1946466293
Short name T183
Test name
Test status
Simulation time 3526909872 ps
CPU time 17.33 seconds
Started Jun 22 04:45:01 PM PDT 24
Finished Jun 22 04:45:18 PM PDT 24
Peak memory 211152 kb
Host smart-4e65c7da-d04a-41d0-9bf5-118a7535f354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946466293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1946466293
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.694901082
Short name T86
Test name
Test status
Simulation time 10247426970 ps
CPU time 35.45 seconds
Started Jun 22 04:45:02 PM PDT 24
Finished Jun 22 04:45:38 PM PDT 24
Peak memory 214476 kb
Host smart-6158b5ae-029b-443d-abed-bd6bbc59086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694901082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.694901082
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3850854690
Short name T136
Test name
Test status
Simulation time 11362426275 ps
CPU time 53.96 seconds
Started Jun 22 04:44:55 PM PDT 24
Finished Jun 22 04:45:50 PM PDT 24
Peak memory 216784 kb
Host smart-ae93e7bc-dab7-476e-a21a-7df861a5de18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850854690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3850854690
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3805330714
Short name T314
Test name
Test status
Simulation time 2101092489 ps
CPU time 15.75 seconds
Started Jun 22 04:45:00 PM PDT 24
Finished Jun 22 04:45:16 PM PDT 24
Peak memory 211124 kb
Host smart-5ccf467b-f4cf-4334-a2c8-e940566c02c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805330714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3805330714
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1345432611
Short name T176
Test name
Test status
Simulation time 27054788018 ps
CPU time 326.28 seconds
Started Jun 22 04:44:56 PM PDT 24
Finished Jun 22 04:50:23 PM PDT 24
Peak memory 236760 kb
Host smart-d1a344ab-afe8-4ab5-934d-6b7503234bae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345432611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1345432611
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2662676923
Short name T304
Test name
Test status
Simulation time 8872767673 ps
CPU time 23.37 seconds
Started Jun 22 04:44:55 PM PDT 24
Finished Jun 22 04:45:19 PM PDT 24
Peak memory 212120 kb
Host smart-c26e4c09-4427-435b-bcad-da6666956521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662676923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2662676923
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4036276795
Short name T131
Test name
Test status
Simulation time 717632885 ps
CPU time 5.47 seconds
Started Jun 22 04:45:01 PM PDT 24
Finished Jun 22 04:45:06 PM PDT 24
Peak memory 211296 kb
Host smart-18400da0-63aa-411a-a622-cf20584eac25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036276795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4036276795
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.908165269
Short name T276
Test name
Test status
Simulation time 7374158329 ps
CPU time 36.47 seconds
Started Jun 22 04:45:00 PM PDT 24
Finished Jun 22 04:45:36 PM PDT 24
Peak memory 214044 kb
Host smart-de3d3a5c-1218-461e-ad3e-183fb978b7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908165269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.908165269
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1930599601
Short name T34
Test name
Test status
Simulation time 39521467107 ps
CPU time 31.61 seconds
Started Jun 22 04:45:01 PM PDT 24
Finished Jun 22 04:45:33 PM PDT 24
Peak memory 217016 kb
Host smart-4ce5ce02-9974-42b2-8674-3a8a8fbaf658
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930599601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1930599601
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.419337607
Short name T348
Test name
Test status
Simulation time 53535122948 ps
CPU time 1015.75 seconds
Started Jun 22 04:45:03 PM PDT 24
Finished Jun 22 05:01:59 PM PDT 24
Peak memory 235720 kb
Host smart-98c5ae94-54fd-4f08-ad4d-37584b6b00c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419337607 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.419337607
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1613122358
Short name T189
Test name
Test status
Simulation time 415857621 ps
CPU time 4.34 seconds
Started Jun 22 04:44:57 PM PDT 24
Finished Jun 22 04:45:01 PM PDT 24
Peak memory 211068 kb
Host smart-1523b021-8cd5-40df-9f60-4503b7fbc55a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613122358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1613122358
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2608752263
Short name T319
Test name
Test status
Simulation time 2944891061 ps
CPU time 70.87 seconds
Started Jun 22 04:44:55 PM PDT 24
Finished Jun 22 04:46:06 PM PDT 24
Peak memory 212600 kb
Host smart-6a29814d-ab98-450c-abf7-07968fd93e8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608752263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2608752263
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.770574703
Short name T198
Test name
Test status
Simulation time 6444034874 ps
CPU time 28.54 seconds
Started Jun 22 04:45:02 PM PDT 24
Finished Jun 22 04:45:30 PM PDT 24
Peak memory 212328 kb
Host smart-a7e75637-5d20-4c19-b665-f251974db8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770574703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.770574703
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4158940996
Short name T277
Test name
Test status
Simulation time 5538412591 ps
CPU time 12.98 seconds
Started Jun 22 04:44:56 PM PDT 24
Finished Jun 22 04:45:09 PM PDT 24
Peak memory 211364 kb
Host smart-f7e3782e-8686-4a41-abbe-6085fac9809c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158940996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4158940996
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3957644411
Short name T365
Test name
Test status
Simulation time 687113389 ps
CPU time 14.24 seconds
Started Jun 22 04:45:02 PM PDT 24
Finished Jun 22 04:45:17 PM PDT 24
Peak memory 213392 kb
Host smart-710f6ae7-564e-413b-a9fb-c0d4ea4ff0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957644411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3957644411
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2661221846
Short name T200
Test name
Test status
Simulation time 239249089 ps
CPU time 7.62 seconds
Started Jun 22 04:44:58 PM PDT 24
Finished Jun 22 04:45:06 PM PDT 24
Peak memory 210924 kb
Host smart-aafb526a-0e06-4121-986b-385d2d5c4054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661221846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2661221846
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4251461159
Short name T67
Test name
Test status
Simulation time 85583620 ps
CPU time 4.36 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:45:12 PM PDT 24
Peak memory 210976 kb
Host smart-5f233051-ad50-484b-b325-8426c844a65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251461159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4251461159
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2237228288
Short name T282
Test name
Test status
Simulation time 4581569113 ps
CPU time 146.23 seconds
Started Jun 22 04:44:58 PM PDT 24
Finished Jun 22 04:47:25 PM PDT 24
Peak memory 212332 kb
Host smart-216095dd-4ea7-4d3b-8f5e-9d3e7c0d79e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237228288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2237228288
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3475752411
Short name T249
Test name
Test status
Simulation time 3623901653 ps
CPU time 21.81 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:45:32 PM PDT 24
Peak memory 211772 kb
Host smart-24fe91d5-9699-4425-a913-15d3c3e0cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475752411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3475752411
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.414866224
Short name T4
Test name
Test status
Simulation time 5494106218 ps
CPU time 12.93 seconds
Started Jun 22 04:45:03 PM PDT 24
Finished Jun 22 04:45:16 PM PDT 24
Peak memory 211364 kb
Host smart-9a5af476-bc74-47e6-8893-4d3d4b857381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414866224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.414866224
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4089025567
Short name T270
Test name
Test status
Simulation time 3124871884 ps
CPU time 15.22 seconds
Started Jun 22 04:45:00 PM PDT 24
Finished Jun 22 04:45:16 PM PDT 24
Peak memory 213388 kb
Host smart-636a48c3-ec3e-417a-a000-eddd3cc8de9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089025567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4089025567
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.933629287
Short name T311
Test name
Test status
Simulation time 682554786 ps
CPU time 29.6 seconds
Started Jun 22 04:44:59 PM PDT 24
Finished Jun 22 04:45:29 PM PDT 24
Peak memory 216360 kb
Host smart-da92edcc-634d-4fb1-8f11-4355d4df3604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933629287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.933629287
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.466980101
Short name T191
Test name
Test status
Simulation time 195628210 ps
CPU time 4.15 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 04:45:09 PM PDT 24
Peak memory 210976 kb
Host smart-07b23340-daa2-4b56-9329-8f2f32f33a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466980101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.466980101
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.804091481
Short name T266
Test name
Test status
Simulation time 9666618013 ps
CPU time 153.09 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 04:47:38 PM PDT 24
Peak memory 232836 kb
Host smart-d54c6db5-0d97-4fc8-bb0a-713f357d04f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804091481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.804091481
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2122818597
Short name T280
Test name
Test status
Simulation time 4117403241 ps
CPU time 33.91 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:43 PM PDT 24
Peak memory 211852 kb
Host smart-84c1d088-8343-4872-816c-aba5a3bfe973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122818597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2122818597
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1054533946
Short name T175
Test name
Test status
Simulation time 597898668 ps
CPU time 7.63 seconds
Started Jun 22 04:45:03 PM PDT 24
Finished Jun 22 04:45:11 PM PDT 24
Peak memory 211228 kb
Host smart-04eb4657-6cb7-4695-bd14-f45fc084673b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054533946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1054533946
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2293389788
Short name T182
Test name
Test status
Simulation time 782725249 ps
CPU time 10.19 seconds
Started Jun 22 04:45:06 PM PDT 24
Finished Jun 22 04:45:17 PM PDT 24
Peak memory 213224 kb
Host smart-21810a2f-d173-4136-811a-87753eb72f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293389788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2293389788
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.688513793
Short name T306
Test name
Test status
Simulation time 2143830143 ps
CPU time 18.29 seconds
Started Jun 22 04:45:04 PM PDT 24
Finished Jun 22 04:45:23 PM PDT 24
Peak memory 213744 kb
Host smart-ede21e30-ad6f-4ca5-beea-14822d803660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688513793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.688513793
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.266193415
Short name T5
Test name
Test status
Simulation time 347934605 ps
CPU time 4.28 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:13 PM PDT 24
Peak memory 211024 kb
Host smart-37a85ee2-e57d-462a-8325-4bf342340725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266193415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.266193415
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2991452710
Short name T312
Test name
Test status
Simulation time 32006615323 ps
CPU time 236.9 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 237468 kb
Host smart-132344a7-aac8-4a64-bc2f-c99902e6b935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991452710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2991452710
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3967835998
Short name T307
Test name
Test status
Simulation time 9233815610 ps
CPU time 24.3 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:45:32 PM PDT 24
Peak memory 212216 kb
Host smart-cb70c938-07ee-4a99-8eee-369d3e9c4d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967835998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3967835998
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1499647608
Short name T272
Test name
Test status
Simulation time 96971851 ps
CPU time 5.63 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:45:16 PM PDT 24
Peak memory 211292 kb
Host smart-cbc8cfde-f01f-47e1-9513-4f1c9ea55888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499647608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1499647608
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1016442576
Short name T127
Test name
Test status
Simulation time 692368720 ps
CPU time 14.3 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:23 PM PDT 24
Peak memory 213540 kb
Host smart-1335a0d2-b6c8-424f-b870-7b236e0e9c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016442576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1016442576
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3654422483
Short name T323
Test name
Test status
Simulation time 2755032829 ps
CPU time 22.25 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:31 PM PDT 24
Peak memory 215968 kb
Host smart-44560eec-4aeb-4666-bffe-a3f6c83ecc3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654422483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3654422483
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4027292459
Short name T287
Test name
Test status
Simulation time 85622268 ps
CPU time 4.36 seconds
Started Jun 22 04:45:03 PM PDT 24
Finished Jun 22 04:45:08 PM PDT 24
Peak memory 211072 kb
Host smart-b3315a0c-51f8-4228-94ac-30ca42238406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027292459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4027292459
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1928887874
Short name T192
Test name
Test status
Simulation time 6818577796 ps
CPU time 152.82 seconds
Started Jun 22 04:45:06 PM PDT 24
Finished Jun 22 04:47:40 PM PDT 24
Peak memory 237120 kb
Host smart-f06a3e3a-4492-49f2-8815-bdb93d71fa42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928887874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1928887874
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3745009087
Short name T196
Test name
Test status
Simulation time 6893863740 ps
CPU time 27.32 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:36 PM PDT 24
Peak memory 212144 kb
Host smart-95b534f6-5dc0-40bb-90c6-03c898664e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745009087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3745009087
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.126025781
Short name T349
Test name
Test status
Simulation time 3814175317 ps
CPU time 16.07 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:45:28 PM PDT 24
Peak memory 211356 kb
Host smart-477ea554-3d11-4e38-bfb2-66a1d2bfc9ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126025781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.126025781
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1534192293
Short name T158
Test name
Test status
Simulation time 8906321171 ps
CPU time 34.45 seconds
Started Jun 22 04:45:04 PM PDT 24
Finished Jun 22 04:45:39 PM PDT 24
Peak memory 213744 kb
Host smart-5ce89c28-5b89-468c-b326-82cd8bd3c453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534192293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1534192293
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.50822445
Short name T290
Test name
Test status
Simulation time 1681440305 ps
CPU time 21.4 seconds
Started Jun 22 04:46:05 PM PDT 24
Finished Jun 22 04:46:27 PM PDT 24
Peak memory 214092 kb
Host smart-4e3eff88-85aa-4642-9f36-9e593a17de3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50822445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.rom_ctrl_stress_all.50822445
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1233798016
Short name T110
Test name
Test status
Simulation time 158613365427 ps
CPU time 2934.28 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 05:34:00 PM PDT 24
Peak memory 241540 kb
Host smart-ad226a1d-666e-426c-ac5c-4a1135b267af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233798016 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1233798016
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4099538970
Short name T356
Test name
Test status
Simulation time 2746109117 ps
CPU time 12.14 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:45:20 PM PDT 24
Peak memory 211192 kb
Host smart-c40f8407-7dec-4323-b3ee-79385993d3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099538970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4099538970
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.958488169
Short name T228
Test name
Test status
Simulation time 14935487791 ps
CPU time 172.49 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:48:01 PM PDT 24
Peak memory 228184 kb
Host smart-0b1c53fd-b8cd-4488-a852-8684c3c0b1bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958488169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.958488169
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2628912933
Short name T139
Test name
Test status
Simulation time 415941770 ps
CPU time 12.48 seconds
Started Jun 22 04:45:24 PM PDT 24
Finished Jun 22 04:45:37 PM PDT 24
Peak memory 211836 kb
Host smart-5b9a4202-c7f8-4d9f-989d-5c1c05d1eab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628912933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2628912933
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3388584696
Short name T300
Test name
Test status
Simulation time 830073863 ps
CPU time 7.16 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 04:45:13 PM PDT 24
Peak memory 211300 kb
Host smart-a4b475da-0ab1-4c47-bc40-9adb79899c97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388584696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3388584696
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.788400101
Short name T203
Test name
Test status
Simulation time 1387790687 ps
CPU time 10.25 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:45:20 PM PDT 24
Peak memory 213884 kb
Host smart-9dca6724-3fba-40b6-869b-044f117449c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788400101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.788400101
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.407982692
Short name T2
Test name
Test status
Simulation time 10231450861 ps
CPU time 58.97 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 04:46:05 PM PDT 24
Peak memory 219364 kb
Host smart-d593f961-77ad-4847-83d1-33678dfa4f76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407982692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.407982692
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4286210826
Short name T291
Test name
Test status
Simulation time 4941441225 ps
CPU time 11.87 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:44:53 PM PDT 24
Peak memory 211120 kb
Host smart-fff59b93-c161-4c8b-a116-bb1dda11f154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286210826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4286210826
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2997184673
Short name T254
Test name
Test status
Simulation time 21216013529 ps
CPU time 259.61 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:49:01 PM PDT 24
Peak memory 237548 kb
Host smart-d63b0a6b-6c64-4cea-b219-64b79808eb8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997184673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2997184673
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.656082182
Short name T60
Test name
Test status
Simulation time 4814022684 ps
CPU time 27.14 seconds
Started Jun 22 04:44:43 PM PDT 24
Finished Jun 22 04:45:10 PM PDT 24
Peak memory 212876 kb
Host smart-75863674-ebcb-44b4-a1fd-da4ca3a966a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656082182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.656082182
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.475993555
Short name T271
Test name
Test status
Simulation time 5924489940 ps
CPU time 13.97 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:45:22 PM PDT 24
Peak memory 211196 kb
Host smart-e2d2f30c-a332-4f40-a672-f0bd8aaea97e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475993555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.475993555
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.14560591
Short name T27
Test name
Test status
Simulation time 4135351708 ps
CPU time 58.88 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:45:39 PM PDT 24
Peak memory 233408 kb
Host smart-d3e2fca9-884c-414f-9d57-5c6a76e7bd73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.14560591
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1013166393
Short name T260
Test name
Test status
Simulation time 6131023658 ps
CPU time 21.63 seconds
Started Jun 22 04:44:42 PM PDT 24
Finished Jun 22 04:45:04 PM PDT 24
Peak memory 213492 kb
Host smart-2cbe1e9d-6480-42e7-92f2-f783ff9003dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013166393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1013166393
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4213063548
Short name T301
Test name
Test status
Simulation time 5151671823 ps
CPU time 35.92 seconds
Started Jun 22 04:44:39 PM PDT 24
Finished Jun 22 04:45:16 PM PDT 24
Peak memory 216028 kb
Host smart-85293c77-c2c1-42de-9142-8e8cdca574a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213063548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4213063548
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3888175059
Short name T343
Test name
Test status
Simulation time 1510669004 ps
CPU time 12.61 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:45:21 PM PDT 24
Peak memory 211120 kb
Host smart-6de30d13-10c6-4470-86bf-c3fc19b7a869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888175059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3888175059
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.298967796
Short name T255
Test name
Test status
Simulation time 151702662965 ps
CPU time 396.33 seconds
Started Jun 22 04:45:06 PM PDT 24
Finished Jun 22 04:51:43 PM PDT 24
Peak memory 233512 kb
Host smart-e8a12ff4-ab3a-42ae-9783-ae6f3cc26472
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298967796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.298967796
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.112013915
Short name T201
Test name
Test status
Simulation time 7146375936 ps
CPU time 20.67 seconds
Started Jun 22 04:45:10 PM PDT 24
Finished Jun 22 04:45:31 PM PDT 24
Peak memory 211308 kb
Host smart-facc4655-293d-4cc2-ae77-4cbdfebe061a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112013915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.112013915
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.142667969
Short name T374
Test name
Test status
Simulation time 611328574 ps
CPU time 6.83 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:45:17 PM PDT 24
Peak memory 211300 kb
Host smart-7464f71a-f9d4-40a3-9b18-23722df7389c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142667969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.142667969
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1779723691
Short name T257
Test name
Test status
Simulation time 2004022788 ps
CPU time 16.09 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:45:26 PM PDT 24
Peak memory 213620 kb
Host smart-0ad9bf9b-60e1-47aa-8f5f-bc4c34423db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779723691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1779723691
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3079739886
Short name T36
Test name
Test status
Simulation time 4212644233 ps
CPU time 51.16 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 04:45:56 PM PDT 24
Peak memory 215208 kb
Host smart-ed70fcd0-8ef7-42f8-9128-a4ddd28ed650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079739886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3079739886
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4263536893
Short name T210
Test name
Test status
Simulation time 1269592524 ps
CPU time 12.25 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:21 PM PDT 24
Peak memory 211032 kb
Host smart-745b3358-713a-4dd9-9054-7621529b247c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263536893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4263536893
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3688785873
Short name T150
Test name
Test status
Simulation time 88158638268 ps
CPU time 441.4 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:52:29 PM PDT 24
Peak memory 225128 kb
Host smart-35daed92-341d-487a-ab36-2bec5cd06284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688785873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3688785873
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.643310189
Short name T151
Test name
Test status
Simulation time 18810654255 ps
CPU time 26.07 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:45:36 PM PDT 24
Peak memory 212192 kb
Host smart-3e379e9f-ae23-4746-8e7a-3f59f20ca843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643310189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.643310189
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1767874417
Short name T273
Test name
Test status
Simulation time 2541562044 ps
CPU time 13.22 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 04:45:19 PM PDT 24
Peak memory 211256 kb
Host smart-2bc342cd-aa19-4be6-a242-2e754c90b600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767874417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1767874417
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4153776702
Short name T226
Test name
Test status
Simulation time 1344361908 ps
CPU time 14.31 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:23 PM PDT 24
Peak memory 212628 kb
Host smart-2713db1e-93ff-4e58-b4b2-ba296c9ea136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153776702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4153776702
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2816942997
Short name T130
Test name
Test status
Simulation time 4468807609 ps
CPU time 35.79 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:44 PM PDT 24
Peak memory 213648 kb
Host smart-eda14971-30ec-45e7-bc0a-82ea38a48641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816942997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2816942997
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1259909249
Short name T54
Test name
Test status
Simulation time 12973952345 ps
CPU time 2731.84 seconds
Started Jun 22 04:45:04 PM PDT 24
Finished Jun 22 05:30:36 PM PDT 24
Peak memory 232204 kb
Host smart-3fb63199-2c67-4b68-96b9-ccceb7774c8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259909249 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1259909249
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2613200880
Short name T31
Test name
Test status
Simulation time 2108245282 ps
CPU time 15.34 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:45:23 PM PDT 24
Peak memory 211128 kb
Host smart-099d6926-58ac-4de8-af38-d11f7c5afa61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613200880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2613200880
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1200240613
Short name T195
Test name
Test status
Simulation time 30445974232 ps
CPU time 206.51 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:48:36 PM PDT 24
Peak memory 237260 kb
Host smart-78ed16e0-954e-4342-908b-4c7c4e3a0b5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200240613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1200240613
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2190020893
Short name T164
Test name
Test status
Simulation time 309462981 ps
CPU time 9.71 seconds
Started Jun 22 04:45:08 PM PDT 24
Finished Jun 22 04:45:18 PM PDT 24
Peak memory 211728 kb
Host smart-2e7455e0-0afe-45af-8de4-c107476e1683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190020893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2190020893
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1375827615
Short name T132
Test name
Test status
Simulation time 1549329450 ps
CPU time 14.08 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 04:45:20 PM PDT 24
Peak memory 211296 kb
Host smart-6975790d-7eb7-4e43-904e-44c4bebac4be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375827615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1375827615
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3565778058
Short name T187
Test name
Test status
Simulation time 1365192443 ps
CPU time 14.22 seconds
Started Jun 22 04:45:06 PM PDT 24
Finished Jun 22 04:45:21 PM PDT 24
Peak memory 213684 kb
Host smart-23b47fd4-4e74-4357-99b3-42a07f3daf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565778058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3565778058
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.442121851
Short name T283
Test name
Test status
Simulation time 656797199 ps
CPU time 18.87 seconds
Started Jun 22 04:45:05 PM PDT 24
Finished Jun 22 04:45:25 PM PDT 24
Peak memory 213244 kb
Host smart-97cd5bd3-987f-458c-bfb1-b09aa1066ace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442121851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.442121851
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2986060823
Short name T288
Test name
Test status
Simulation time 212388591667 ps
CPU time 4487.75 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 05:59:58 PM PDT 24
Peak memory 235836 kb
Host smart-7ea5aab1-f6af-4d61-8e12-c941d6e84c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986060823 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2986060823
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.789473683
Short name T167
Test name
Test status
Simulation time 1356510702 ps
CPU time 12.22 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 04:45:28 PM PDT 24
Peak memory 211032 kb
Host smart-84bce650-8643-44f3-957b-1beb3da8c3be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789473683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.789473683
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.570716200
Short name T143
Test name
Test status
Simulation time 87064165680 ps
CPU time 229.76 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:49:01 PM PDT 24
Peak memory 233536 kb
Host smart-48f8c47d-51ac-4953-9082-b433a4673479
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570716200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.570716200
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3739278770
Short name T330
Test name
Test status
Simulation time 342260718 ps
CPU time 12.13 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:45:24 PM PDT 24
Peak memory 211804 kb
Host smart-a7271581-44fa-4f38-844e-a4718010ccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739278770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3739278770
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1878860607
Short name T153
Test name
Test status
Simulation time 188967558 ps
CPU time 5.41 seconds
Started Jun 22 04:45:12 PM PDT 24
Finished Jun 22 04:45:18 PM PDT 24
Peak memory 211292 kb
Host smart-bcd107c2-4cb1-47cf-8cb0-789e5b46c8af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878860607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1878860607
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4181437184
Short name T209
Test name
Test status
Simulation time 4293284770 ps
CPU time 24.16 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:45:34 PM PDT 24
Peak memory 213120 kb
Host smart-e40a089b-f7c2-430a-b86a-e3bb5b52316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181437184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4181437184
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.113099941
Short name T339
Test name
Test status
Simulation time 6143799552 ps
CPU time 16.44 seconds
Started Jun 22 04:45:07 PM PDT 24
Finished Jun 22 04:45:24 PM PDT 24
Peak memory 212408 kb
Host smart-4680520f-1ddb-4b4a-8143-2f2936c24195
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113099941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.113099941
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3011760767
Short name T342
Test name
Test status
Simulation time 3192116551 ps
CPU time 9 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:45:21 PM PDT 24
Peak memory 211148 kb
Host smart-199e5011-f312-4e2c-ac53-314115af54e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011760767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3011760767
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2240499132
Short name T238
Test name
Test status
Simulation time 306349622668 ps
CPU time 205.83 seconds
Started Jun 22 04:45:12 PM PDT 24
Finished Jun 22 04:48:39 PM PDT 24
Peak memory 213644 kb
Host smart-d9a52e87-9c35-4861-ac9a-ad796beb1515
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240499132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2240499132
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3874041987
Short name T24
Test name
Test status
Simulation time 20511142036 ps
CPU time 23.91 seconds
Started Jun 22 04:45:10 PM PDT 24
Finished Jun 22 04:45:35 PM PDT 24
Peak memory 213444 kb
Host smart-9eb2e03a-aa5e-4f1d-bd2d-9144a7fe953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874041987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3874041987
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1391154766
Short name T109
Test name
Test status
Simulation time 1934816554 ps
CPU time 16.11 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 04:45:33 PM PDT 24
Peak memory 211300 kb
Host smart-a0c36ddc-2758-4127-a9f5-0ce969eddfd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391154766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1391154766
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3250553854
Short name T81
Test name
Test status
Simulation time 753884029 ps
CPU time 10.23 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:45:22 PM PDT 24
Peak memory 213908 kb
Host smart-5a515d72-6472-4564-963d-b1c6cf5ff590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250553854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3250553854
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2955253198
Short name T310
Test name
Test status
Simulation time 4448206801 ps
CPU time 37.88 seconds
Started Jun 22 04:45:10 PM PDT 24
Finished Jun 22 04:45:48 PM PDT 24
Peak memory 216128 kb
Host smart-c8bf2497-6f66-4b77-80ec-f82e646e50df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955253198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2955253198
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.745767556
Short name T258
Test name
Test status
Simulation time 974971215 ps
CPU time 6.88 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 04:45:23 PM PDT 24
Peak memory 211032 kb
Host smart-d340e5d5-1879-4333-9634-c3ebc74d37ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745767556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.745767556
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.96595937
Short name T219
Test name
Test status
Simulation time 76468991546 ps
CPU time 306.46 seconds
Started Jun 22 04:45:14 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 237640 kb
Host smart-e030a1e3-e6ea-4de6-b285-934952fb8626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96595937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co
rrupt_sig_fatal_chk.96595937
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.730942195
Short name T322
Test name
Test status
Simulation time 3108929525 ps
CPU time 27.84 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:45:39 PM PDT 24
Peak memory 211940 kb
Host smart-086fc023-729d-42e5-ac81-464211a24ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730942195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.730942195
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.799768664
Short name T259
Test name
Test status
Simulation time 345281743 ps
CPU time 5.82 seconds
Started Jun 22 04:45:12 PM PDT 24
Finished Jun 22 04:45:19 PM PDT 24
Peak memory 211228 kb
Host smart-b424831c-937c-463f-81dc-422af4180996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799768664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.799768664
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2037171217
Short name T318
Test name
Test status
Simulation time 12100016476 ps
CPU time 30.61 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:45:42 PM PDT 24
Peak memory 214092 kb
Host smart-ecab2ba7-8205-4ff6-8225-e9dd25758a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037171217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2037171217
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.960605890
Short name T218
Test name
Test status
Simulation time 414317463 ps
CPU time 22.4 seconds
Started Jun 22 04:45:09 PM PDT 24
Finished Jun 22 04:45:32 PM PDT 24
Peak memory 214140 kb
Host smart-441d41d2-55e4-45a8-9f41-53c7dc10a820
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960605890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.960605890
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2941240879
Short name T366
Test name
Test status
Simulation time 116386820413 ps
CPU time 2534.11 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 05:27:26 PM PDT 24
Peak memory 235728 kb
Host smart-5f49a059-ab11-45f0-8e6c-3ff94a2ab49d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941240879 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2941240879
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2724301813
Short name T231
Test name
Test status
Simulation time 4260229095 ps
CPU time 16.74 seconds
Started Jun 22 04:45:13 PM PDT 24
Finished Jun 22 04:45:30 PM PDT 24
Peak memory 211096 kb
Host smart-c1c71d3c-755b-4876-b28d-cc8915051df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724301813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2724301813
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1392287437
Short name T234
Test name
Test status
Simulation time 72552678130 ps
CPU time 207.9 seconds
Started Jun 22 04:45:13 PM PDT 24
Finished Jun 22 04:48:41 PM PDT 24
Peak memory 224488 kb
Host smart-a3f87983-eff1-4176-baac-7a326e4762bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392287437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1392287437
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3308739386
Short name T309
Test name
Test status
Simulation time 6425871843 ps
CPU time 19.89 seconds
Started Jun 22 04:45:14 PM PDT 24
Finished Jun 22 04:45:34 PM PDT 24
Peak memory 212184 kb
Host smart-d6c0a1c1-f488-49b3-b13b-693423bb09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308739386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3308739386
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.386258190
Short name T57
Test name
Test status
Simulation time 1637398709 ps
CPU time 15.1 seconds
Started Jun 22 04:45:14 PM PDT 24
Finished Jun 22 04:45:30 PM PDT 24
Peak memory 211300 kb
Host smart-83b5fd0c-5940-4dfd-929d-efd6ddda42b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386258190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.386258190
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3750652772
Short name T297
Test name
Test status
Simulation time 24663083801 ps
CPU time 31.19 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 04:45:48 PM PDT 24
Peak memory 214472 kb
Host smart-43bb70f6-af1b-49e0-bd42-b834eedda952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750652772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3750652772
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3336188777
Short name T188
Test name
Test status
Simulation time 26127497755 ps
CPU time 42.28 seconds
Started Jun 22 04:45:12 PM PDT 24
Finished Jun 22 04:45:55 PM PDT 24
Peak memory 216992 kb
Host smart-705fefb8-27ba-4a52-9059-22d559a349c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336188777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3336188777
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1714573394
Short name T335
Test name
Test status
Simulation time 4752308702 ps
CPU time 11.14 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:45:23 PM PDT 24
Peak memory 211212 kb
Host smart-abdf76f0-c2a8-4130-a156-5d53a70b70fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714573394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1714573394
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1330733367
Short name T371
Test name
Test status
Simulation time 34822395440 ps
CPU time 134.19 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 04:47:31 PM PDT 24
Peak memory 234632 kb
Host smart-e81ee860-d5d1-4b00-a0cf-83d647d23ecc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330733367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1330733367
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3804941262
Short name T252
Test name
Test status
Simulation time 3426866986 ps
CPU time 30.5 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 04:45:47 PM PDT 24
Peak memory 211820 kb
Host smart-f3980423-7d5f-42a5-831d-f7d735ada4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804941262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3804941262
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.780106631
Short name T286
Test name
Test status
Simulation time 1888992356 ps
CPU time 16.79 seconds
Started Jun 22 04:45:11 PM PDT 24
Finished Jun 22 04:45:29 PM PDT 24
Peak memory 211104 kb
Host smart-068d0ee8-1ee5-4f0e-8576-0b07ae134d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780106631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.780106631
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.754203776
Short name T56
Test name
Test status
Simulation time 2472919655 ps
CPU time 14.31 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 04:45:31 PM PDT 24
Peak memory 213840 kb
Host smart-37610fc1-7d45-4f74-ac14-7a8f923987bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754203776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.754203776
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.869133719
Short name T35
Test name
Test status
Simulation time 11526961331 ps
CPU time 16.38 seconds
Started Jun 22 04:45:17 PM PDT 24
Finished Jun 22 04:45:34 PM PDT 24
Peak memory 216104 kb
Host smart-3681f455-61ce-42bc-abed-f460e23961fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869133719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.869133719
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.117830755
Short name T161
Test name
Test status
Simulation time 998431915 ps
CPU time 10.64 seconds
Started Jun 22 04:45:25 PM PDT 24
Finished Jun 22 04:45:37 PM PDT 24
Peak memory 211036 kb
Host smart-d0881c68-95e1-4358-a401-1f1b36f5e3a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117830755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.117830755
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2502184704
Short name T125
Test name
Test status
Simulation time 2066317311 ps
CPU time 109.75 seconds
Started Jun 22 04:45:14 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 212544 kb
Host smart-37f20c78-f67f-40b8-bcea-9eaebf021119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502184704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2502184704
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1688085781
Short name T178
Test name
Test status
Simulation time 333556867 ps
CPU time 9.36 seconds
Started Jun 22 04:45:24 PM PDT 24
Finished Jun 22 04:45:33 PM PDT 24
Peak memory 211512 kb
Host smart-d692dff2-c867-47ee-b54c-ee7ebafaadb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688085781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1688085781
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1855495128
Short name T233
Test name
Test status
Simulation time 5357038244 ps
CPU time 11.85 seconds
Started Jun 22 04:45:12 PM PDT 24
Finished Jun 22 04:45:25 PM PDT 24
Peak memory 211256 kb
Host smart-73596fb9-f368-49ae-af6d-de6fa949a535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855495128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1855495128
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.977740805
Short name T340
Test name
Test status
Simulation time 21250408241 ps
CPU time 33.22 seconds
Started Jun 22 04:45:12 PM PDT 24
Finished Jun 22 04:45:46 PM PDT 24
Peak memory 214360 kb
Host smart-b1afda4b-9954-4c18-ae14-b9767f0f74bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977740805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.977740805
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2973103842
Short name T327
Test name
Test status
Simulation time 2729996430 ps
CPU time 18.42 seconds
Started Jun 22 04:45:17 PM PDT 24
Finished Jun 22 04:45:36 PM PDT 24
Peak memory 211072 kb
Host smart-8295c0de-6562-416a-b12e-08810e906588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973103842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2973103842
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1337095184
Short name T33
Test name
Test status
Simulation time 169173055 ps
CPU time 5.45 seconds
Started Jun 22 04:45:22 PM PDT 24
Finished Jun 22 04:45:27 PM PDT 24
Peak memory 211136 kb
Host smart-e10ac284-247e-4a28-8e0a-430469002ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337095184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1337095184
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2151651685
Short name T213
Test name
Test status
Simulation time 27706625633 ps
CPU time 288.14 seconds
Started Jun 22 04:45:17 PM PDT 24
Finished Jun 22 04:50:05 PM PDT 24
Peak memory 237676 kb
Host smart-06f5f570-1a8b-4630-a08b-64eb26e41690
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151651685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2151651685
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2583256358
Short name T268
Test name
Test status
Simulation time 336220863 ps
CPU time 9.45 seconds
Started Jun 22 04:45:23 PM PDT 24
Finished Jun 22 04:45:33 PM PDT 24
Peak memory 212684 kb
Host smart-3c281d82-335e-4040-856b-5e21fbd58725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583256358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2583256358
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4056579834
Short name T133
Test name
Test status
Simulation time 492023678 ps
CPU time 5.5 seconds
Started Jun 22 04:45:23 PM PDT 24
Finished Jun 22 04:45:29 PM PDT 24
Peak memory 211296 kb
Host smart-a7871daf-7784-47ed-9991-7775b69a11fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056579834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4056579834
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2149278641
Short name T84
Test name
Test status
Simulation time 3141045462 ps
CPU time 35.19 seconds
Started Jun 22 04:45:19 PM PDT 24
Finished Jun 22 04:45:55 PM PDT 24
Peak memory 213644 kb
Host smart-028e1e31-994f-484a-8d3d-83950a4ea1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149278641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2149278641
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2596938565
Short name T284
Test name
Test status
Simulation time 1569743992 ps
CPU time 14.31 seconds
Started Jun 22 04:45:25 PM PDT 24
Finished Jun 22 04:45:40 PM PDT 24
Peak memory 211652 kb
Host smart-e80ea940-edbd-48a9-8c72-7fb23da9d774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596938565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2596938565
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2732364836
Short name T52
Test name
Test status
Simulation time 45981313346 ps
CPU time 1597.5 seconds
Started Jun 22 04:45:19 PM PDT 24
Finished Jun 22 05:11:57 PM PDT 24
Peak memory 235668 kb
Host smart-1f70f2de-7d58-4ca5-9c19-7ee628e8bb6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732364836 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2732364836
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.398551495
Short name T235
Test name
Test status
Simulation time 2317201570 ps
CPU time 11.32 seconds
Started Jun 22 04:44:47 PM PDT 24
Finished Jun 22 04:44:58 PM PDT 24
Peak memory 211032 kb
Host smart-3dc539db-e38b-4a8f-a311-f4681b53f349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398551495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.398551495
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1877326116
Short name T7
Test name
Test status
Simulation time 8702502995 ps
CPU time 166.02 seconds
Started Jun 22 04:44:47 PM PDT 24
Finished Jun 22 04:47:33 PM PDT 24
Peak memory 234600 kb
Host smart-0f6f3646-2e2b-4704-9594-e28c07a60511
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877326116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1877326116
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.858125627
Short name T338
Test name
Test status
Simulation time 4361399251 ps
CPU time 26.68 seconds
Started Jun 22 04:44:42 PM PDT 24
Finished Jun 22 04:45:09 PM PDT 24
Peak memory 212364 kb
Host smart-4a290b73-358a-4db2-a306-0cfe1e269e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858125627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.858125627
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2339965150
Short name T26
Test name
Test status
Simulation time 1750345746 ps
CPU time 82.6 seconds
Started Jun 22 04:44:42 PM PDT 24
Finished Jun 22 04:46:05 PM PDT 24
Peak memory 240024 kb
Host smart-296e08b4-a9a7-48bb-a6b6-6d7a523448bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339965150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2339965150
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3432030211
Short name T82
Test name
Test status
Simulation time 532036476 ps
CPU time 14.54 seconds
Started Jun 22 04:44:44 PM PDT 24
Finished Jun 22 04:44:59 PM PDT 24
Peak memory 213592 kb
Host smart-dbfa08e2-1f11-4291-9857-8c3b2d983455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432030211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3432030211
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1627257465
Short name T262
Test name
Test status
Simulation time 14563690563 ps
CPU time 44.3 seconds
Started Jun 22 04:44:40 PM PDT 24
Finished Jun 22 04:45:25 PM PDT 24
Peak memory 214256 kb
Host smart-4f433eec-8d44-4106-bcc5-3b1a776b4c03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627257465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1627257465
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.818544554
Short name T159
Test name
Test status
Simulation time 2026172083 ps
CPU time 14.61 seconds
Started Jun 22 04:45:22 PM PDT 24
Finished Jun 22 04:45:37 PM PDT 24
Peak memory 211140 kb
Host smart-0634f01d-942a-44e5-aa99-67cc43479ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818544554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.818544554
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2707666735
Short name T354
Test name
Test status
Simulation time 83744181694 ps
CPU time 243.46 seconds
Started Jun 22 04:45:25 PM PDT 24
Finished Jun 22 04:49:29 PM PDT 24
Peak memory 237684 kb
Host smart-717a168f-187b-4591-bb50-debed171a5de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707666735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2707666735
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4121879992
Short name T364
Test name
Test status
Simulation time 7833759452 ps
CPU time 21.15 seconds
Started Jun 22 04:45:19 PM PDT 24
Finished Jun 22 04:45:41 PM PDT 24
Peak memory 212400 kb
Host smart-5666d4b5-9531-4546-af64-bb13926aba68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121879992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4121879992
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1392658976
Short name T230
Test name
Test status
Simulation time 101833274 ps
CPU time 5.73 seconds
Started Jun 22 04:45:20 PM PDT 24
Finished Jun 22 04:45:26 PM PDT 24
Peak memory 211288 kb
Host smart-d53c2fa3-fbca-4f39-8083-9736e72292e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392658976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1392658976
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3362492559
Short name T11
Test name
Test status
Simulation time 8616716395 ps
CPU time 22.53 seconds
Started Jun 22 04:45:19 PM PDT 24
Finished Jun 22 04:45:42 PM PDT 24
Peak memory 213808 kb
Host smart-6e570c65-5f13-4332-b74b-1a3be1c1841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362492559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3362492559
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1577444031
Short name T214
Test name
Test status
Simulation time 2743975693 ps
CPU time 33.49 seconds
Started Jun 22 04:45:21 PM PDT 24
Finished Jun 22 04:45:55 PM PDT 24
Peak memory 216380 kb
Host smart-ebbc2168-9969-4943-8e8a-ae277c07572a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577444031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1577444031
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2757030356
Short name T66
Test name
Test status
Simulation time 346886614 ps
CPU time 4.24 seconds
Started Jun 22 04:45:24 PM PDT 24
Finished Jun 22 04:45:29 PM PDT 24
Peak memory 211352 kb
Host smart-33b157ef-cf0b-4d07-ba28-56121b16cbf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757030356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2757030356
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3262865382
Short name T298
Test name
Test status
Simulation time 246942833133 ps
CPU time 279.95 seconds
Started Jun 22 04:45:20 PM PDT 24
Finished Jun 22 04:50:01 PM PDT 24
Peak memory 234224 kb
Host smart-cbe1539f-21ac-440c-833d-0f988b270fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262865382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3262865382
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1674082105
Short name T135
Test name
Test status
Simulation time 1942588214 ps
CPU time 21.36 seconds
Started Jun 22 04:45:16 PM PDT 24
Finished Jun 22 04:45:39 PM PDT 24
Peak memory 211904 kb
Host smart-dd054335-d2e8-4370-bd31-43ee07611b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674082105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1674082105
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1201246566
Short name T146
Test name
Test status
Simulation time 138384936 ps
CPU time 5.76 seconds
Started Jun 22 04:45:25 PM PDT 24
Finished Jun 22 04:45:32 PM PDT 24
Peak memory 211196 kb
Host smart-84906817-340d-40de-8ae8-d1aa114de00f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201246566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1201246566
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1521225315
Short name T223
Test name
Test status
Simulation time 192826421 ps
CPU time 10 seconds
Started Jun 22 04:45:22 PM PDT 24
Finished Jun 22 04:45:32 PM PDT 24
Peak memory 213708 kb
Host smart-7e962426-188d-43be-933a-447daed7e906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521225315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1521225315
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.867090144
Short name T232
Test name
Test status
Simulation time 655949924 ps
CPU time 17.7 seconds
Started Jun 22 04:45:22 PM PDT 24
Finished Jun 22 04:45:40 PM PDT 24
Peak memory 214156 kb
Host smart-aedf81d5-26e0-4f33-a72b-8436bcb8b5e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867090144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.867090144
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3996991279
Short name T55
Test name
Test status
Simulation time 38830206741 ps
CPU time 367.59 seconds
Started Jun 22 04:45:23 PM PDT 24
Finished Jun 22 04:51:31 PM PDT 24
Peak memory 227668 kb
Host smart-b88309fb-d5a7-40d8-adb8-38b902821c5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996991279 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3996991279
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.411771530
Short name T216
Test name
Test status
Simulation time 85870949 ps
CPU time 4.26 seconds
Started Jun 22 04:45:25 PM PDT 24
Finished Jun 22 04:45:30 PM PDT 24
Peak memory 211032 kb
Host smart-6a034eeb-469a-4b88-8565-fb59030eef06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411771530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.411771530
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.313464134
Short name T184
Test name
Test status
Simulation time 515570603488 ps
CPU time 447.21 seconds
Started Jun 22 04:45:24 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 234744 kb
Host smart-faf68074-fa1e-4f81-8838-01d07d0cdbc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313464134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.313464134
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2947067261
Short name T240
Test name
Test status
Simulation time 1515298606 ps
CPU time 19.12 seconds
Started Jun 22 04:45:24 PM PDT 24
Finished Jun 22 04:45:44 PM PDT 24
Peak memory 211856 kb
Host smart-aee2e347-e7e1-431a-893f-abd5a7ab28f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947067261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2947067261
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2715595026
Short name T247
Test name
Test status
Simulation time 7617946009 ps
CPU time 11.4 seconds
Started Jun 22 04:45:24 PM PDT 24
Finished Jun 22 04:45:37 PM PDT 24
Peak memory 211292 kb
Host smart-0ddfa137-651b-480d-ad81-c530fabf33ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715595026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2715595026
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1477646720
Short name T350
Test name
Test status
Simulation time 5198130385 ps
CPU time 17.48 seconds
Started Jun 22 04:45:25 PM PDT 24
Finished Jun 22 04:45:43 PM PDT 24
Peak memory 213572 kb
Host smart-15c29f14-7c5f-4844-9592-cca3561390d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477646720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1477646720
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3034534797
Short name T370
Test name
Test status
Simulation time 3822322977 ps
CPU time 21.57 seconds
Started Jun 22 04:45:26 PM PDT 24
Finished Jun 22 04:45:48 PM PDT 24
Peak memory 216668 kb
Host smart-57dd9969-f3ee-42bc-9045-929aadfbf31d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034534797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3034534797
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1567114080
Short name T12
Test name
Test status
Simulation time 247887750488 ps
CPU time 1636.94 seconds
Started Jun 22 04:45:26 PM PDT 24
Finished Jun 22 05:12:44 PM PDT 24
Peak memory 235852 kb
Host smart-055cd663-ebe3-4cdc-860e-d60b3091b3f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567114080 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1567114080
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3196079924
Short name T360
Test name
Test status
Simulation time 1932417752 ps
CPU time 15.91 seconds
Started Jun 22 04:45:32 PM PDT 24
Finished Jun 22 04:45:49 PM PDT 24
Peak memory 211032 kb
Host smart-d9b71df5-892d-4cd1-a1ec-e8d277e34490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196079924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3196079924
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2829151740
Short name T40
Test name
Test status
Simulation time 179194163065 ps
CPU time 242.88 seconds
Started Jun 22 04:45:24 PM PDT 24
Finished Jun 22 04:49:27 PM PDT 24
Peak memory 236200 kb
Host smart-bd6de09e-e7f5-4656-87a6-6283a256b278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829151740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2829151740
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1081138633
Short name T333
Test name
Test status
Simulation time 5987676273 ps
CPU time 13.87 seconds
Started Jun 22 04:45:23 PM PDT 24
Finished Jun 22 04:45:37 PM PDT 24
Peak memory 211256 kb
Host smart-892afc41-3b43-43eb-aa46-c6a80d90f6d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081138633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1081138633
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2560642057
Short name T162
Test name
Test status
Simulation time 11926126180 ps
CPU time 32.09 seconds
Started Jun 22 04:45:25 PM PDT 24
Finished Jun 22 04:45:58 PM PDT 24
Peak memory 214232 kb
Host smart-cc7ee15a-647e-479e-b656-4fe11f8ce493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560642057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2560642057
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2299632049
Short name T279
Test name
Test status
Simulation time 464403161 ps
CPU time 16.23 seconds
Started Jun 22 04:45:25 PM PDT 24
Finished Jun 22 04:45:41 PM PDT 24
Peak memory 214112 kb
Host smart-8bced9e6-d36b-4810-840a-a77e26ba80b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299632049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2299632049
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.772357788
Short name T53
Test name
Test status
Simulation time 175133361091 ps
CPU time 1393.85 seconds
Started Jun 22 04:45:33 PM PDT 24
Finished Jun 22 05:08:47 PM PDT 24
Peak memory 235740 kb
Host smart-c5e816ba-9f01-47a2-9eb9-12060fbffdee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772357788 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.772357788
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3629890730
Short name T138
Test name
Test status
Simulation time 6867810688 ps
CPU time 14.72 seconds
Started Jun 22 04:45:31 PM PDT 24
Finished Jun 22 04:45:46 PM PDT 24
Peak memory 211400 kb
Host smart-0933e52f-34a0-4db7-ac6f-3e52a0a9e717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629890730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3629890730
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3522867019
Short name T124
Test name
Test status
Simulation time 24586330889 ps
CPU time 241.8 seconds
Started Jun 22 04:45:33 PM PDT 24
Finished Jun 22 04:49:35 PM PDT 24
Peak memory 234792 kb
Host smart-63668534-b0c4-4e43-9c6d-a9cd16ab19b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522867019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3522867019
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.541911189
Short name T325
Test name
Test status
Simulation time 11585774123 ps
CPU time 26.68 seconds
Started Jun 22 04:45:32 PM PDT 24
Finished Jun 22 04:45:59 PM PDT 24
Peak memory 212200 kb
Host smart-9953e92d-3ecd-4a41-868f-45a3df5d0a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541911189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.541911189
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.888153374
Short name T299
Test name
Test status
Simulation time 7670030649 ps
CPU time 15.49 seconds
Started Jun 22 04:45:32 PM PDT 24
Finished Jun 22 04:45:48 PM PDT 24
Peak memory 211364 kb
Host smart-c0ca7bdf-5f26-4827-9026-f8f458b1fd93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888153374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.888153374
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1040162723
Short name T185
Test name
Test status
Simulation time 7987431199 ps
CPU time 29.59 seconds
Started Jun 22 04:45:31 PM PDT 24
Finished Jun 22 04:46:02 PM PDT 24
Peak memory 214112 kb
Host smart-cfe214c2-0352-419d-87f6-39f819a933b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040162723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1040162723
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4242653982
Short name T166
Test name
Test status
Simulation time 13108768887 ps
CPU time 52.87 seconds
Started Jun 22 04:45:32 PM PDT 24
Finished Jun 22 04:46:25 PM PDT 24
Peak memory 215864 kb
Host smart-e1959087-b5ed-4a7d-b833-597f8a5ab96d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242653982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4242653982
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.826067308
Short name T190
Test name
Test status
Simulation time 1503411075 ps
CPU time 12.29 seconds
Started Jun 22 04:45:43 PM PDT 24
Finished Jun 22 04:45:56 PM PDT 24
Peak memory 211140 kb
Host smart-ea1c7ac8-3fc8-4ad5-ba7b-2f279248e884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826067308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.826067308
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1615904466
Short name T37
Test name
Test status
Simulation time 74633968559 ps
CPU time 222.94 seconds
Started Jun 22 04:45:31 PM PDT 24
Finished Jun 22 04:49:14 PM PDT 24
Peak memory 236916 kb
Host smart-5fbffd06-2e9d-4f8f-9dda-191d8234eef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615904466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1615904466
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2841845827
Short name T180
Test name
Test status
Simulation time 2949695741 ps
CPU time 21.4 seconds
Started Jun 22 04:45:32 PM PDT 24
Finished Jun 22 04:45:54 PM PDT 24
Peak memory 211856 kb
Host smart-82a5cca0-6382-4325-9cfa-845a09281b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841845827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2841845827
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2455460390
Short name T285
Test name
Test status
Simulation time 93873440 ps
CPU time 5.41 seconds
Started Jun 22 04:45:32 PM PDT 24
Finished Jun 22 04:45:38 PM PDT 24
Peak memory 211236 kb
Host smart-8b2a54e0-2ef4-4326-bab7-b2b55dd55e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2455460390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2455460390
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1509431644
Short name T313
Test name
Test status
Simulation time 2674551517 ps
CPU time 16.29 seconds
Started Jun 22 04:45:31 PM PDT 24
Finished Jun 22 04:45:48 PM PDT 24
Peak memory 211616 kb
Host smart-814d8f8e-ef8f-4165-8bc1-078a6015d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509431644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1509431644
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.970635422
Short name T186
Test name
Test status
Simulation time 3326144138 ps
CPU time 40.72 seconds
Started Jun 22 04:45:34 PM PDT 24
Finished Jun 22 04:46:15 PM PDT 24
Peak memory 216556 kb
Host smart-2cdd60c7-a0ab-4372-99eb-050f90e0e8e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970635422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.970635422
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3506913035
Short name T243
Test name
Test status
Simulation time 1237917167 ps
CPU time 8.4 seconds
Started Jun 22 04:45:39 PM PDT 24
Finished Jun 22 04:45:49 PM PDT 24
Peak memory 211140 kb
Host smart-34766b06-7bc5-4ee0-a03f-989111e871b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506913035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3506913035
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4007151443
Short name T227
Test name
Test status
Simulation time 40151102649 ps
CPU time 312.43 seconds
Started Jun 22 04:45:39 PM PDT 24
Finished Jun 22 04:50:52 PM PDT 24
Peak memory 225500 kb
Host smart-40b4a679-4b3c-410c-b456-cf373409c910
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007151443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4007151443
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4047981988
Short name T344
Test name
Test status
Simulation time 1479115977 ps
CPU time 19.01 seconds
Started Jun 22 04:45:39 PM PDT 24
Finished Jun 22 04:46:00 PM PDT 24
Peak memory 211832 kb
Host smart-29164ccf-5e06-4d52-91ef-481f77282927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047981988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4047981988
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1192433041
Short name T129
Test name
Test status
Simulation time 4224939587 ps
CPU time 15.06 seconds
Started Jun 22 04:45:41 PM PDT 24
Finished Jun 22 04:45:57 PM PDT 24
Peak memory 211364 kb
Host smart-d573df63-dc9e-4092-a180-0ed61aae0668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192433041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1192433041
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.916799982
Short name T326
Test name
Test status
Simulation time 13873592712 ps
CPU time 36.34 seconds
Started Jun 22 04:45:40 PM PDT 24
Finished Jun 22 04:46:18 PM PDT 24
Peak memory 213988 kb
Host smart-0192b552-c383-41b8-9179-12af386a45d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916799982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.916799982
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.571053849
Short name T269
Test name
Test status
Simulation time 20886037907 ps
CPU time 77.43 seconds
Started Jun 22 04:45:38 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 219280 kb
Host smart-0898540c-73b4-4e0f-8e8b-8fb2b7b77e05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571053849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.571053849
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2228157863
Short name T145
Test name
Test status
Simulation time 332329550 ps
CPU time 6.97 seconds
Started Jun 22 04:45:41 PM PDT 24
Finished Jun 22 04:45:48 PM PDT 24
Peak memory 211140 kb
Host smart-0192e7b5-7046-4462-87a4-c4772f5ad650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228157863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2228157863
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1664273273
Short name T13
Test name
Test status
Simulation time 61034179008 ps
CPU time 289.29 seconds
Started Jun 22 04:45:38 PM PDT 24
Finished Jun 22 04:50:28 PM PDT 24
Peak memory 233612 kb
Host smart-988ab736-042c-41ac-a699-cbc501466e22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664273273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1664273273
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3831209416
Short name T137
Test name
Test status
Simulation time 16727546020 ps
CPU time 31.02 seconds
Started Jun 22 04:45:43 PM PDT 24
Finished Jun 22 04:46:15 PM PDT 24
Peak memory 212116 kb
Host smart-f378ebe4-1044-4b0c-8758-ee148c59dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831209416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3831209416
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3886197413
Short name T207
Test name
Test status
Simulation time 2181725901 ps
CPU time 13.08 seconds
Started Jun 22 04:45:38 PM PDT 24
Finished Jun 22 04:45:52 PM PDT 24
Peak memory 211364 kb
Host smart-701ac5b5-e72a-48e7-b740-a970de782f3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886197413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3886197413
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4053959580
Short name T345
Test name
Test status
Simulation time 4455721534 ps
CPU time 32.58 seconds
Started Jun 22 04:45:44 PM PDT 24
Finished Jun 22 04:46:17 PM PDT 24
Peak memory 213404 kb
Host smart-bf6bd9d9-aff5-409c-a935-11b7173882b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053959580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4053959580
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3665055211
Short name T142
Test name
Test status
Simulation time 6695327510 ps
CPU time 23.6 seconds
Started Jun 22 04:45:40 PM PDT 24
Finished Jun 22 04:46:05 PM PDT 24
Peak memory 214272 kb
Host smart-7e988ae8-3882-4a15-aef1-16140570d312
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665055211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3665055211
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2804079860
Short name T248
Test name
Test status
Simulation time 1199524731 ps
CPU time 11.13 seconds
Started Jun 22 04:45:40 PM PDT 24
Finished Jun 22 04:45:52 PM PDT 24
Peak memory 211096 kb
Host smart-cd41e7af-5be4-4a0c-a089-fef8f245178c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804079860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2804079860
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3750069472
Short name T315
Test name
Test status
Simulation time 96124278130 ps
CPU time 534.61 seconds
Started Jun 22 04:45:39 PM PDT 24
Finished Jun 22 04:54:34 PM PDT 24
Peak memory 224796 kb
Host smart-3a73a091-ac29-42c5-a388-e67ad5185c90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750069472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3750069472
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2291880354
Short name T134
Test name
Test status
Simulation time 18696553069 ps
CPU time 34.56 seconds
Started Jun 22 04:45:40 PM PDT 24
Finished Jun 22 04:46:16 PM PDT 24
Peak memory 212132 kb
Host smart-c9bc1cd4-c069-4fa5-8f3f-635d8b292a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291880354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2291880354
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3063364110
Short name T229
Test name
Test status
Simulation time 1327342839 ps
CPU time 13.2 seconds
Started Jun 22 04:45:37 PM PDT 24
Finished Jun 22 04:45:51 PM PDT 24
Peak memory 211516 kb
Host smart-cdf32dd4-0a40-4fb5-81c2-ebbbde9afcbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063364110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3063364110
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3368977841
Short name T369
Test name
Test status
Simulation time 3871091562 ps
CPU time 33.2 seconds
Started Jun 22 04:45:39 PM PDT 24
Finished Jun 22 04:46:13 PM PDT 24
Peak memory 213256 kb
Host smart-6828eb1f-bd6a-46cb-8ebd-01887fc31186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368977841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3368977841
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2097978132
Short name T28
Test name
Test status
Simulation time 15040876056 ps
CPU time 61.88 seconds
Started Jun 22 04:45:38 PM PDT 24
Finished Jun 22 04:46:41 PM PDT 24
Peak memory 218068 kb
Host smart-85048ec0-f88a-4fa1-8007-4c87c812b2bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097978132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2097978132
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.391499135
Short name T253
Test name
Test status
Simulation time 168678859 ps
CPU time 4.27 seconds
Started Jun 22 04:45:45 PM PDT 24
Finished Jun 22 04:45:49 PM PDT 24
Peak memory 211140 kb
Host smart-89734f04-54cc-45ff-8d54-8afce67afb14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391499135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.391499135
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2089639324
Short name T246
Test name
Test status
Simulation time 146432393616 ps
CPU time 324.51 seconds
Started Jun 22 04:45:47 PM PDT 24
Finished Jun 22 04:51:12 PM PDT 24
Peak memory 236604 kb
Host smart-60dd090e-f0da-4b03-ad14-5f9b6e1cf33f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089639324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2089639324
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3022424385
Short name T222
Test name
Test status
Simulation time 16329532243 ps
CPU time 30.52 seconds
Started Jun 22 04:45:46 PM PDT 24
Finished Jun 22 04:46:17 PM PDT 24
Peak memory 212208 kb
Host smart-4fa63315-0260-424d-9fce-dabc1d026e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022424385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3022424385
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1536082746
Short name T351
Test name
Test status
Simulation time 13037903405 ps
CPU time 11.2 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:46:05 PM PDT 24
Peak memory 211256 kb
Host smart-7d1b99d1-957a-4fb4-9f8f-f9422bcb66de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536082746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1536082746
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.729247781
Short name T215
Test name
Test status
Simulation time 19355078785 ps
CPU time 44.42 seconds
Started Jun 22 04:45:40 PM PDT 24
Finished Jun 22 04:46:26 PM PDT 24
Peak memory 213668 kb
Host smart-d8c79e49-fd23-4da2-8589-fae1e27452f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729247781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.729247781
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.882506359
Short name T317
Test name
Test status
Simulation time 27534024126 ps
CPU time 48.89 seconds
Started Jun 22 04:45:48 PM PDT 24
Finished Jun 22 04:46:37 PM PDT 24
Peak memory 217016 kb
Host smart-d5fe3fea-1d33-45b5-a92d-320463b2f339
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882506359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.882506359
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2316200966
Short name T156
Test name
Test status
Simulation time 2261670063 ps
CPU time 16.55 seconds
Started Jun 22 04:44:49 PM PDT 24
Finished Jun 22 04:45:06 PM PDT 24
Peak memory 211408 kb
Host smart-c811331b-65b7-41eb-8eb5-e426d40f6930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316200966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2316200966
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1903712022
Short name T303
Test name
Test status
Simulation time 12803128217 ps
CPU time 174.21 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:47:45 PM PDT 24
Peak memory 212540 kb
Host smart-9000bdd1-b114-4b5c-a3dc-1651ef0cfda7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903712022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1903712022
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2008757559
Short name T242
Test name
Test status
Simulation time 1234476358 ps
CPU time 17.69 seconds
Started Jun 22 04:44:47 PM PDT 24
Finished Jun 22 04:45:06 PM PDT 24
Peak memory 211812 kb
Host smart-597d8d89-c861-492e-bcd7-1e0a5a623cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008757559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2008757559
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3309003740
Short name T173
Test name
Test status
Simulation time 134240956 ps
CPU time 5.4 seconds
Started Jun 22 04:44:51 PM PDT 24
Finished Jun 22 04:44:57 PM PDT 24
Peak memory 211284 kb
Host smart-7b395e54-e9f3-43a1-bfef-58c80afed135
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309003740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3309003740
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3870548838
Short name T18
Test name
Test status
Simulation time 6367406830 ps
CPU time 53.8 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:45 PM PDT 24
Peak memory 233584 kb
Host smart-079bed62-cc52-4370-84c4-e9c021e97993
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870548838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3870548838
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2857964015
Short name T171
Test name
Test status
Simulation time 2026475848 ps
CPU time 17.69 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:09 PM PDT 24
Peak memory 212976 kb
Host smart-30883eba-c7c4-42fd-a074-1f70e066d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857964015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2857964015
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3385701433
Short name T208
Test name
Test status
Simulation time 5211380486 ps
CPU time 51.68 seconds
Started Jun 22 04:44:47 PM PDT 24
Finished Jun 22 04:45:40 PM PDT 24
Peak memory 219348 kb
Host smart-fe8cdc40-0083-496d-b8e8-125a2b12cdcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385701433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3385701433
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.921273733
Short name T261
Test name
Test status
Simulation time 2077015624 ps
CPU time 17.51 seconds
Started Jun 22 04:45:47 PM PDT 24
Finished Jun 22 04:46:05 PM PDT 24
Peak memory 211064 kb
Host smart-99647deb-31d2-4345-b837-29fcd3126dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921273733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.921273733
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2779611476
Short name T30
Test name
Test status
Simulation time 3994437806 ps
CPU time 108.68 seconds
Started Jun 22 04:45:47 PM PDT 24
Finished Jun 22 04:47:36 PM PDT 24
Peak memory 237612 kb
Host smart-05d075cd-af6a-4dbe-831b-01577806114b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779611476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2779611476
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2381170277
Short name T47
Test name
Test status
Simulation time 341317264 ps
CPU time 9.41 seconds
Started Jun 22 04:45:46 PM PDT 24
Finished Jun 22 04:45:56 PM PDT 24
Peak memory 212024 kb
Host smart-b59fa1ef-a789-46b9-b788-b92db83e4eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381170277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2381170277
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2365676990
Short name T294
Test name
Test status
Simulation time 1986593494 ps
CPU time 16.52 seconds
Started Jun 22 04:45:49 PM PDT 24
Finished Jun 22 04:46:06 PM PDT 24
Peak memory 211288 kb
Host smart-b822583d-43ef-48b2-ab9c-da86496105e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365676990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2365676990
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1000016051
Short name T353
Test name
Test status
Simulation time 5169241550 ps
CPU time 19.69 seconds
Started Jun 22 04:45:45 PM PDT 24
Finished Jun 22 04:46:05 PM PDT 24
Peak memory 213680 kb
Host smart-532b7487-3a13-44ee-8dab-8abf92e9dee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000016051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1000016051
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.664746702
Short name T305
Test name
Test status
Simulation time 41145634448 ps
CPU time 86.73 seconds
Started Jun 22 04:45:46 PM PDT 24
Finished Jun 22 04:47:13 PM PDT 24
Peak memory 218616 kb
Host smart-2c190609-7ea7-4f71-b265-eb80582aa5ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664746702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.664746702
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.4023973027
Short name T332
Test name
Test status
Simulation time 55952188744 ps
CPU time 2192.92 seconds
Started Jun 22 04:45:45 PM PDT 24
Finished Jun 22 05:22:18 PM PDT 24
Peak memory 231528 kb
Host smart-e4f20c9c-2d96-4600-8e52-f65471cc945c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023973027 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.4023973027
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3124905586
Short name T20
Test name
Test status
Simulation time 85445927 ps
CPU time 4.26 seconds
Started Jun 22 04:45:46 PM PDT 24
Finished Jun 22 04:45:50 PM PDT 24
Peak memory 211084 kb
Host smart-6ad08238-e3c1-40be-babe-8d6b930b9908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124905586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3124905586
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2605176281
Short name T334
Test name
Test status
Simulation time 2167989035 ps
CPU time 128.76 seconds
Started Jun 22 04:45:47 PM PDT 24
Finished Jun 22 04:47:56 PM PDT 24
Peak memory 236604 kb
Host smart-ae9e6c9d-0322-4c28-aef7-6c1089dcd005
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605176281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2605176281
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.699732056
Short name T275
Test name
Test status
Simulation time 2731330149 ps
CPU time 25.62 seconds
Started Jun 22 04:45:49 PM PDT 24
Finished Jun 22 04:46:15 PM PDT 24
Peak memory 211736 kb
Host smart-63e689f5-cb3c-44a9-af94-f7fab0b57761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699732056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.699732056
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1048193206
Short name T206
Test name
Test status
Simulation time 6177942022 ps
CPU time 15.76 seconds
Started Jun 22 04:45:49 PM PDT 24
Finished Jun 22 04:46:05 PM PDT 24
Peak memory 211236 kb
Host smart-5f13f293-95cc-411a-92c8-125f6c1c2b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048193206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1048193206
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3073038563
Short name T181
Test name
Test status
Simulation time 344519531 ps
CPU time 10.36 seconds
Started Jun 22 04:45:48 PM PDT 24
Finished Jun 22 04:45:59 PM PDT 24
Peak memory 213880 kb
Host smart-8990de82-85c5-48bd-8602-0f21900b8fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073038563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3073038563
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3114399713
Short name T126
Test name
Test status
Simulation time 13395332678 ps
CPU time 48.56 seconds
Started Jun 22 04:45:44 PM PDT 24
Finished Jun 22 04:46:33 PM PDT 24
Peak memory 219352 kb
Host smart-6180dd18-73bf-40ce-b439-1a6a7bcd370a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114399713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3114399713
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3676239011
Short name T23
Test name
Test status
Simulation time 25222927562 ps
CPU time 907.25 seconds
Started Jun 22 04:45:47 PM PDT 24
Finished Jun 22 05:00:54 PM PDT 24
Peak memory 234792 kb
Host smart-5b28a940-691a-4cde-82fc-57b6887fd189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676239011 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3676239011
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1772193926
Short name T278
Test name
Test status
Simulation time 1940213049 ps
CPU time 7.44 seconds
Started Jun 22 04:45:55 PM PDT 24
Finished Jun 22 04:46:03 PM PDT 24
Peak memory 211140 kb
Host smart-739c6288-3075-44ce-bce5-817dd5b3eb32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772193926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1772193926
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.251278207
Short name T352
Test name
Test status
Simulation time 93438286118 ps
CPU time 220.34 seconds
Started Jun 22 04:45:52 PM PDT 24
Finished Jun 22 04:49:33 PM PDT 24
Peak memory 233608 kb
Host smart-8bd13a1e-06e3-40c8-9640-2abb38d6f1d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251278207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.251278207
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3512245378
Short name T172
Test name
Test status
Simulation time 170606569 ps
CPU time 9.25 seconds
Started Jun 22 04:45:52 PM PDT 24
Finished Jun 22 04:46:02 PM PDT 24
Peak memory 211868 kb
Host smart-ff126921-d7ff-4c79-882d-f81e2d2cf590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512245378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3512245378
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1723305291
Short name T14
Test name
Test status
Simulation time 98453039 ps
CPU time 5.72 seconds
Started Jun 22 04:45:45 PM PDT 24
Finished Jun 22 04:45:51 PM PDT 24
Peak memory 211180 kb
Host smart-31e07e80-29da-4230-b7b7-923fa65b598f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723305291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1723305291
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.382465898
Short name T331
Test name
Test status
Simulation time 1498405772 ps
CPU time 14.72 seconds
Started Jun 22 04:45:46 PM PDT 24
Finished Jun 22 04:46:01 PM PDT 24
Peak memory 213216 kb
Host smart-2ff6929c-147b-4aba-a6d7-b59230e13a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382465898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.382465898
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.79652087
Short name T80
Test name
Test status
Simulation time 9638959475 ps
CPU time 59.82 seconds
Started Jun 22 04:45:45 PM PDT 24
Finished Jun 22 04:46:45 PM PDT 24
Peak memory 217068 kb
Host smart-24ee4ec5-0a84-45f3-baa9-0edf8b24a2e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79652087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.rom_ctrl_stress_all.79652087
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1095779603
Short name T302
Test name
Test status
Simulation time 50586381278 ps
CPU time 2556.31 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 05:28:31 PM PDT 24
Peak memory 235844 kb
Host smart-2b4d6818-22e8-4978-9563-f91c59780da1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095779603 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1095779603
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3396413677
Short name T69
Test name
Test status
Simulation time 936671949 ps
CPU time 10.1 seconds
Started Jun 22 04:45:55 PM PDT 24
Finished Jun 22 04:46:06 PM PDT 24
Peak memory 211140 kb
Host smart-46932cfd-70a9-4c43-80ab-f73577e56dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396413677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3396413677
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1766845601
Short name T263
Test name
Test status
Simulation time 451460545912 ps
CPU time 284.83 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 228368 kb
Host smart-576f49aa-5e94-4202-99bb-e1618a306811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766845601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1766845601
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3414475609
Short name T361
Test name
Test status
Simulation time 19189163742 ps
CPU time 34.33 seconds
Started Jun 22 04:45:52 PM PDT 24
Finished Jun 22 04:46:27 PM PDT 24
Peak memory 212212 kb
Host smart-540fa750-783e-4ca8-aa32-47872cb65705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414475609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3414475609
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3085437118
Short name T321
Test name
Test status
Simulation time 435873988 ps
CPU time 6.7 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:46:00 PM PDT 24
Peak memory 211300 kb
Host smart-75927ac3-8675-4776-b626-10075f6f3f40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085437118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3085437118
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.527398294
Short name T274
Test name
Test status
Simulation time 691904388 ps
CPU time 10.09 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 04:46:05 PM PDT 24
Peak memory 213388 kb
Host smart-bd85c0ce-cb15-47a3-91e1-99d6f4bca5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527398294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.527398294
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1343854232
Short name T347
Test name
Test status
Simulation time 2621911421 ps
CPU time 11.82 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 04:46:07 PM PDT 24
Peak memory 211204 kb
Host smart-9eb4ff3c-b222-4336-93ac-4a533477cf6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343854232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1343854232
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3451976469
Short name T197
Test name
Test status
Simulation time 49332072359 ps
CPU time 232.61 seconds
Started Jun 22 04:45:55 PM PDT 24
Finished Jun 22 04:49:48 PM PDT 24
Peak memory 237592 kb
Host smart-3956328a-e48b-4da5-a690-ea2a41975acc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451976469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3451976469
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2929893456
Short name T346
Test name
Test status
Simulation time 4572163186 ps
CPU time 26.27 seconds
Started Jun 22 04:45:55 PM PDT 24
Finished Jun 22 04:46:22 PM PDT 24
Peak memory 212324 kb
Host smart-9cf76646-3eb1-4192-bd9d-51b75803af63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929893456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2929893456
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3800272855
Short name T8
Test name
Test status
Simulation time 544172431 ps
CPU time 6.5 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 04:46:01 PM PDT 24
Peak memory 211292 kb
Host smart-343bed2d-faea-47ff-82f4-315411d45489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800272855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3800272855
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3011420669
Short name T244
Test name
Test status
Simulation time 16405109755 ps
CPU time 36.17 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:46:31 PM PDT 24
Peak memory 214220 kb
Host smart-339ffb0f-a17e-4af2-b44d-7345c54ea33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011420669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3011420669
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1109193176
Short name T225
Test name
Test status
Simulation time 2409120666 ps
CPU time 18.96 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:46:13 PM PDT 24
Peak memory 214252 kb
Host smart-3c7d755c-7d29-4fd5-bbd5-0abcd8f834ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109193176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1109193176
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3645968354
Short name T44
Test name
Test status
Simulation time 208191599203 ps
CPU time 1940.45 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 05:18:16 PM PDT 24
Peak memory 236112 kb
Host smart-d4293abd-a4a6-45bd-b012-3b3a3dec4137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645968354 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3645968354
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3166293205
Short name T359
Test name
Test status
Simulation time 5649114848 ps
CPU time 8.71 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 04:46:03 PM PDT 24
Peak memory 211204 kb
Host smart-3b1bd7f7-ab1e-4af2-af10-4a50fd0d4700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166293205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3166293205
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3032794773
Short name T38
Test name
Test status
Simulation time 111670450752 ps
CPU time 206.73 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 04:49:21 PM PDT 24
Peak memory 238052 kb
Host smart-cc9821d6-b587-41ce-aaf8-39300569bfca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032794773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3032794773
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2571478722
Short name T45
Test name
Test status
Simulation time 8909476795 ps
CPU time 32.53 seconds
Started Jun 22 04:45:54 PM PDT 24
Finished Jun 22 04:46:27 PM PDT 24
Peak memory 213088 kb
Host smart-d0c1b607-374a-49dc-9512-a7d6088f34a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571478722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2571478722
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3483754153
Short name T293
Test name
Test status
Simulation time 2211301342 ps
CPU time 17.57 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:46:11 PM PDT 24
Peak memory 211364 kb
Host smart-caac5a36-416a-4cc9-b428-a56e59344531
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483754153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3483754153
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.699707743
Short name T155
Test name
Test status
Simulation time 3674765152 ps
CPU time 18.54 seconds
Started Jun 22 04:46:18 PM PDT 24
Finished Jun 22 04:46:37 PM PDT 24
Peak memory 213676 kb
Host smart-505758d7-e395-41b4-a6c1-79ef85ffd233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699707743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.699707743
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.563228897
Short name T170
Test name
Test status
Simulation time 95264970819 ps
CPU time 82.14 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 214652 kb
Host smart-7d42ee71-ac00-42ae-a37f-0309272479c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563228897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.563228897
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2161854602
Short name T111
Test name
Test status
Simulation time 80931239972 ps
CPU time 3522.75 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 05:44:37 PM PDT 24
Peak memory 246360 kb
Host smart-7e9b06c8-d14c-4ec5-ab69-63da0ce56c2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161854602 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2161854602
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1923844791
Short name T250
Test name
Test status
Simulation time 2964237298 ps
CPU time 9.21 seconds
Started Jun 22 04:46:03 PM PDT 24
Finished Jun 22 04:46:13 PM PDT 24
Peak memory 211184 kb
Host smart-17b629bf-c714-4118-8c2b-459a0b224d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923844791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1923844791
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3278929716
Short name T256
Test name
Test status
Simulation time 12130473462 ps
CPU time 116.74 seconds
Started Jun 22 04:45:56 PM PDT 24
Finished Jun 22 04:47:53 PM PDT 24
Peak memory 237660 kb
Host smart-dee5752b-4017-42ba-b8e6-f2bfa9c96a48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278929716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3278929716
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.972067731
Short name T6
Test name
Test status
Simulation time 5624756579 ps
CPU time 19.93 seconds
Started Jun 22 04:46:01 PM PDT 24
Finished Jun 22 04:46:22 PM PDT 24
Peak memory 212112 kb
Host smart-9ae6eb62-664d-4764-a032-1f925a321c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972067731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.972067731
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3912081583
Short name T220
Test name
Test status
Simulation time 1854858592 ps
CPU time 15.76 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:46:10 PM PDT 24
Peak memory 211184 kb
Host smart-38925b76-1fda-4137-a69e-ea2159a9c637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912081583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3912081583
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2917938415
Short name T169
Test name
Test status
Simulation time 11019436381 ps
CPU time 28.22 seconds
Started Jun 22 04:45:53 PM PDT 24
Finished Jun 22 04:46:22 PM PDT 24
Peak memory 214240 kb
Host smart-2c6fc4a6-cba3-4a4b-8307-145080b1907b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917938415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2917938415
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1375918433
Short name T199
Test name
Test status
Simulation time 88392045 ps
CPU time 4.32 seconds
Started Jun 22 04:47:06 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 211084 kb
Host smart-ee03a093-d39f-499b-9e28-1b48a9ea2508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375918433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1375918433
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1129910879
Short name T221
Test name
Test status
Simulation time 1376802996 ps
CPU time 85.57 seconds
Started Jun 22 04:46:05 PM PDT 24
Finished Jun 22 04:47:32 PM PDT 24
Peak memory 237624 kb
Host smart-4312f4a4-ce13-4dbe-8c7d-b547e8b7e233
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129910879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1129910879
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3364108688
Short name T46
Test name
Test status
Simulation time 333871938 ps
CPU time 9.51 seconds
Started Jun 22 04:46:03 PM PDT 24
Finished Jun 22 04:46:13 PM PDT 24
Peak memory 211884 kb
Host smart-6ce05cac-1927-4eb3-bbca-5e3badf507e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364108688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3364108688
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.786203224
Short name T245
Test name
Test status
Simulation time 541228359 ps
CPU time 6.6 seconds
Started Jun 22 04:46:01 PM PDT 24
Finished Jun 22 04:46:08 PM PDT 24
Peak memory 211192 kb
Host smart-d2905474-9b5c-4919-85a2-9f424120e954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786203224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.786203224
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3819667031
Short name T237
Test name
Test status
Simulation time 13852141806 ps
CPU time 29.02 seconds
Started Jun 22 04:46:03 PM PDT 24
Finished Jun 22 04:46:32 PM PDT 24
Peak memory 214400 kb
Host smart-88df4726-7ce0-4c27-9012-b007a299b0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819667031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3819667031
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.52989789
Short name T316
Test name
Test status
Simulation time 10428646252 ps
CPU time 65.14 seconds
Started Jun 22 04:46:05 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 219348 kb
Host smart-ab67963d-57d3-42f5-a55a-42f16d162828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52989789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.rom_ctrl_stress_all.52989789
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3820690201
Short name T179
Test name
Test status
Simulation time 347362918 ps
CPU time 4.39 seconds
Started Jun 22 04:46:04 PM PDT 24
Finished Jun 22 04:46:08 PM PDT 24
Peak memory 211032 kb
Host smart-88e418e4-5070-4af9-be69-baae686681eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820690201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3820690201
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.137694381
Short name T368
Test name
Test status
Simulation time 78682130216 ps
CPU time 173.8 seconds
Started Jun 22 04:46:03 PM PDT 24
Finished Jun 22 04:48:57 PM PDT 24
Peak memory 212492 kb
Host smart-e107b887-e712-4182-8b7e-b6b926fc2ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137694381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.137694381
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1499064103
Short name T50
Test name
Test status
Simulation time 2408973344 ps
CPU time 18.15 seconds
Started Jun 22 04:46:02 PM PDT 24
Finished Jun 22 04:46:21 PM PDT 24
Peak memory 211788 kb
Host smart-ba010176-30dc-4a66-ad2a-47740191b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499064103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1499064103
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3894490609
Short name T202
Test name
Test status
Simulation time 790127564 ps
CPU time 5.94 seconds
Started Jun 22 04:46:04 PM PDT 24
Finished Jun 22 04:46:11 PM PDT 24
Peak memory 211244 kb
Host smart-3963c00b-23d0-4299-83fe-a9bfbd256839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894490609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3894490609
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.670936747
Short name T281
Test name
Test status
Simulation time 3702661764 ps
CPU time 22.59 seconds
Started Jun 22 04:46:01 PM PDT 24
Finished Jun 22 04:46:24 PM PDT 24
Peak memory 213720 kb
Host smart-8acade50-6a42-4439-a87c-0a99d98716f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670936747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.670936747
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3146185285
Short name T328
Test name
Test status
Simulation time 2981659427 ps
CPU time 40.05 seconds
Started Jun 22 04:46:02 PM PDT 24
Finished Jun 22 04:46:42 PM PDT 24
Peak memory 213980 kb
Host smart-c58c4c2c-efc4-4b2e-bdee-c66a3f5ccd09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146185285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3146185285
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2501637177
Short name T157
Test name
Test status
Simulation time 2140769582 ps
CPU time 7.58 seconds
Started Jun 22 04:46:05 PM PDT 24
Finished Jun 22 04:46:14 PM PDT 24
Peak memory 211128 kb
Host smart-2188d73d-ec76-49a2-84fb-ee9d487c46ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501637177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2501637177
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3985854982
Short name T42
Test name
Test status
Simulation time 68828503231 ps
CPU time 228.89 seconds
Started Jun 22 04:46:02 PM PDT 24
Finished Jun 22 04:49:51 PM PDT 24
Peak memory 237680 kb
Host smart-127866ab-dd4a-4308-beed-2c30d21763c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985854982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3985854982
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.477835284
Short name T372
Test name
Test status
Simulation time 2949366040 ps
CPU time 27.45 seconds
Started Jun 22 04:46:09 PM PDT 24
Finished Jun 22 04:46:38 PM PDT 24
Peak memory 211788 kb
Host smart-44aafd64-5b5d-4262-8be5-f64e54dc5352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477835284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.477835284
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2665953897
Short name T337
Test name
Test status
Simulation time 391267503 ps
CPU time 5.57 seconds
Started Jun 22 04:46:04 PM PDT 24
Finished Jun 22 04:46:10 PM PDT 24
Peak memory 211192 kb
Host smart-01add693-b7fa-4079-9fe9-96a99c17aeb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665953897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2665953897
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2536716567
Short name T308
Test name
Test status
Simulation time 3038145045 ps
CPU time 28.84 seconds
Started Jun 22 04:46:04 PM PDT 24
Finished Jun 22 04:46:34 PM PDT 24
Peak memory 211356 kb
Host smart-54a16e3f-30f3-4851-be04-80c32f9c0f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536716567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2536716567
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2061866923
Short name T341
Test name
Test status
Simulation time 8956378622 ps
CPU time 80.31 seconds
Started Jun 22 04:46:01 PM PDT 24
Finished Jun 22 04:47:22 PM PDT 24
Peak memory 216620 kb
Host smart-45d59dbf-7137-4370-be54-40b01def091d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061866923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2061866923
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.984971594
Short name T373
Test name
Test status
Simulation time 28083831297 ps
CPU time 827.28 seconds
Started Jun 22 04:46:00 PM PDT 24
Finished Jun 22 04:59:48 PM PDT 24
Peak memory 235852 kb
Host smart-35f4597b-9576-44a2-b678-ec54df8e06dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984971594 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.984971594
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2739434384
Short name T264
Test name
Test status
Simulation time 2306910323 ps
CPU time 11.21 seconds
Started Jun 22 04:44:48 PM PDT 24
Finished Jun 22 04:45:00 PM PDT 24
Peak memory 211076 kb
Host smart-f5edc7ad-3f89-4ed1-9deb-c6bb49e45df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739434384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2739434384
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3131624896
Short name T154
Test name
Test status
Simulation time 20197412606 ps
CPU time 82.51 seconds
Started Jun 22 04:44:47 PM PDT 24
Finished Jun 22 04:46:10 PM PDT 24
Peak memory 236632 kb
Host smart-a75b252f-45b2-4224-b79e-1dc4c955f372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131624896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3131624896
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.392859736
Short name T152
Test name
Test status
Simulation time 1037505331 ps
CPU time 11.14 seconds
Started Jun 22 04:44:48 PM PDT 24
Finished Jun 22 04:44:59 PM PDT 24
Peak memory 211836 kb
Host smart-d1018bbf-6dd0-486d-b880-b91ca1ff8751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392859736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.392859736
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1281806038
Short name T212
Test name
Test status
Simulation time 374767349 ps
CPU time 5.27 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:44:57 PM PDT 24
Peak memory 211116 kb
Host smart-891741b0-30f6-40ac-9d4c-2c25c574d46e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281806038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1281806038
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2012730549
Short name T85
Test name
Test status
Simulation time 11177947408 ps
CPU time 34.85 seconds
Started Jun 22 04:44:49 PM PDT 24
Finished Jun 22 04:45:25 PM PDT 24
Peak memory 213944 kb
Host smart-0660453f-a695-432a-9d4d-78e2ead4e5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012730549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2012730549
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2898012593
Short name T295
Test name
Test status
Simulation time 1152909419 ps
CPU time 15.94 seconds
Started Jun 22 04:44:47 PM PDT 24
Finished Jun 22 04:45:03 PM PDT 24
Peak memory 216212 kb
Host smart-12e19c5b-5a2b-4b6f-8062-94a08875756a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898012593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2898012593
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3749058540
Short name T204
Test name
Test status
Simulation time 376619881 ps
CPU time 6.85 seconds
Started Jun 22 04:44:49 PM PDT 24
Finished Jun 22 04:44:56 PM PDT 24
Peak memory 211012 kb
Host smart-3c68dbf2-1c3b-4d91-b776-cd5937a8519f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749058540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3749058540
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3973757879
Short name T41
Test name
Test status
Simulation time 71778197239 ps
CPU time 246.77 seconds
Started Jun 22 04:44:49 PM PDT 24
Finished Jun 22 04:48:56 PM PDT 24
Peak memory 236956 kb
Host smart-759fac04-4f39-4133-8a6a-25aea314b7d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973757879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3973757879
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3695451821
Short name T177
Test name
Test status
Simulation time 7483329342 ps
CPU time 31.25 seconds
Started Jun 22 04:44:51 PM PDT 24
Finished Jun 22 04:45:23 PM PDT 24
Peak memory 212356 kb
Host smart-91665468-7491-4050-a1ef-f5c5c10e5308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695451821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3695451821
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.968016129
Short name T141
Test name
Test status
Simulation time 2232155548 ps
CPU time 17.62 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:08 PM PDT 24
Peak memory 211360 kb
Host smart-760d5f3e-ff77-48a1-a5c0-3a7e650fe5fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968016129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.968016129
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1157973612
Short name T15
Test name
Test status
Simulation time 8183521591 ps
CPU time 23.99 seconds
Started Jun 22 04:45:30 PM PDT 24
Finished Jun 22 04:45:55 PM PDT 24
Peak memory 214092 kb
Host smart-caef324e-f7b5-403c-b21b-da5868809ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157973612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1157973612
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1961464731
Short name T168
Test name
Test status
Simulation time 4980885503 ps
CPU time 16.23 seconds
Started Jun 22 04:44:46 PM PDT 24
Finished Jun 22 04:45:03 PM PDT 24
Peak memory 212572 kb
Host smart-66ea0ac5-20d0-4284-ac72-eb921e92980a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961464731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1961464731
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3455951550
Short name T48
Test name
Test status
Simulation time 53452459349 ps
CPU time 3605.75 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 05:44:56 PM PDT 24
Peak memory 235848 kb
Host smart-0db86fba-267e-4513-b075-43a28df4d5ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455951550 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3455951550
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1962027682
Short name T267
Test name
Test status
Simulation time 297700094 ps
CPU time 4.31 seconds
Started Jun 22 04:44:49 PM PDT 24
Finished Jun 22 04:44:54 PM PDT 24
Peak memory 211340 kb
Host smart-9efdb3fd-35ea-4f08-9560-88cab51956c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962027682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1962027682
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2281033203
Short name T217
Test name
Test status
Simulation time 23732449874 ps
CPU time 175.7 seconds
Started Jun 22 04:44:49 PM PDT 24
Finished Jun 22 04:47:45 PM PDT 24
Peak memory 232724 kb
Host smart-4c9f8bcf-aceb-4459-9cc9-edc1e7f2109e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281033203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2281033203
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2730231936
Short name T148
Test name
Test status
Simulation time 17635757867 ps
CPU time 30.67 seconds
Started Jun 22 04:44:51 PM PDT 24
Finished Jun 22 04:45:23 PM PDT 24
Peak memory 212132 kb
Host smart-fa223136-5b96-43ce-85e9-6fba4975eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730231936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2730231936
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.809323622
Short name T224
Test name
Test status
Simulation time 5620105730 ps
CPU time 13.27 seconds
Started Jun 22 04:44:47 PM PDT 24
Finished Jun 22 04:45:01 PM PDT 24
Peak memory 211252 kb
Host smart-7e142b34-09ef-465e-80ae-5a24f1b65ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809323622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.809323622
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1480491671
Short name T140
Test name
Test status
Simulation time 39440577734 ps
CPU time 31.64 seconds
Started Jun 22 04:44:48 PM PDT 24
Finished Jun 22 04:45:20 PM PDT 24
Peak memory 214192 kb
Host smart-bf3521b2-1490-474a-9e83-97e399c4a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480491671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1480491671
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2135748706
Short name T32
Test name
Test status
Simulation time 12607347672 ps
CPU time 32.15 seconds
Started Jun 22 04:44:54 PM PDT 24
Finished Jun 22 04:45:26 PM PDT 24
Peak memory 216928 kb
Host smart-58ca574a-0202-43df-8133-e546aa4c86a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135748706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2135748706
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.328183342
Short name T163
Test name
Test status
Simulation time 844815384 ps
CPU time 9 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:00 PM PDT 24
Peak memory 210976 kb
Host smart-39eacf02-9072-448e-ad71-689b06ec1e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328183342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.328183342
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.407911083
Short name T324
Test name
Test status
Simulation time 35243988863 ps
CPU time 185.41 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:47:57 PM PDT 24
Peak memory 234784 kb
Host smart-b12d175e-15de-4d0f-835b-1761360cfd20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407911083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.407911083
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.511993939
Short name T296
Test name
Test status
Simulation time 11948047120 ps
CPU time 27.17 seconds
Started Jun 22 04:44:47 PM PDT 24
Finished Jun 22 04:45:15 PM PDT 24
Peak memory 212156 kb
Host smart-bd1b77c7-5acb-4e50-9f76-f161435b1fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511993939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.511993939
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3641746645
Short name T149
Test name
Test status
Simulation time 5623023464 ps
CPU time 14.86 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:05 PM PDT 24
Peak memory 211360 kb
Host smart-9cbe354d-9c28-41e6-916e-11bf0310435d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641746645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3641746645
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.205738212
Short name T83
Test name
Test status
Simulation time 1436686925 ps
CPU time 12.9 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:04 PM PDT 24
Peak memory 213436 kb
Host smart-8c6b7e1f-657e-48cb-8042-392a06cba556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205738212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.205738212
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3980676301
Short name T367
Test name
Test status
Simulation time 114194954 ps
CPU time 8.77 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:00 PM PDT 24
Peak memory 211080 kb
Host smart-be5a05fd-03bf-4716-b2e9-6991e0b98296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980676301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3980676301
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.528260186
Short name T147
Test name
Test status
Simulation time 1034608595 ps
CPU time 4.28 seconds
Started Jun 22 04:44:48 PM PDT 24
Finished Jun 22 04:44:53 PM PDT 24
Peak memory 211124 kb
Host smart-9ed02b58-969d-4089-9b9b-4cb43cde22c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528260186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.528260186
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.310626003
Short name T355
Test name
Test status
Simulation time 101112946127 ps
CPU time 291.34 seconds
Started Jun 22 04:44:51 PM PDT 24
Finished Jun 22 04:49:43 PM PDT 24
Peak memory 225548 kb
Host smart-aa8cc97a-7ad8-4a06-97f8-1c01eb47d57f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310626003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.310626003
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1028866846
Short name T29
Test name
Test status
Simulation time 12486814867 ps
CPU time 26.58 seconds
Started Jun 22 04:44:51 PM PDT 24
Finished Jun 22 04:45:18 PM PDT 24
Peak memory 212120 kb
Host smart-cb61c4df-616f-4bb5-96a5-f16d75f4d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028866846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1028866846
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2115097558
Short name T336
Test name
Test status
Simulation time 1322304448 ps
CPU time 5.73 seconds
Started Jun 22 04:44:46 PM PDT 24
Finished Jun 22 04:44:52 PM PDT 24
Peak memory 211296 kb
Host smart-c6ed96bb-9961-43e0-8bfe-164da2c9a376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115097558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2115097558
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1428248099
Short name T3
Test name
Test status
Simulation time 13318332593 ps
CPU time 37.79 seconds
Started Jun 22 04:44:50 PM PDT 24
Finished Jun 22 04:45:29 PM PDT 24
Peak memory 213508 kb
Host smart-f3b7b2f6-ed15-47cb-a719-87969f8eab28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428248099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1428248099
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1708459378
Short name T193
Test name
Test status
Simulation time 12419685210 ps
CPU time 36.88 seconds
Started Jun 22 04:44:54 PM PDT 24
Finished Jun 22 04:45:31 PM PDT 24
Peak memory 213996 kb
Host smart-15890ea5-e3f6-4f1c-8537-bd15b010281f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708459378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1708459378
Directory /workspace/9.rom_ctrl_stress_all/latest
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