Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2647137

1

T2

81

T3

230

T4

106

full_word

1700032

1

T2

4

T3

25

T4

12

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4346879	1			T2	85		T3	255		T4	118
auto[TlIntgErrCmd]	99	1			T64	2		T65	9		T66	4
auto[TlIntgErrData]	104	1			T64	3		T65	7		T66	2
auto[TlIntgErrBoth]	87	1			T64	5		T65	4		T66	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692383

1

T2

85

T3

255

T4

118

auto[1]

3654786

1

T20

200927

T21

317300

T22

58722

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	289639	1			T2	81		T3	230		T4	106
auto[TlIntgErrNone]	partial	auto[1]	2357223	1			T20	130954		T21	205502		T22	37328
auto[TlIntgErrNone]	full_word	auto[0]	402615	1			T2	4		T3	25		T4	12
auto[TlIntgErrNone]	full_word	auto[1]	1297402	1			T20	69973		T21	111798		T22	21394
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T65	3		T66	2		T114	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T64	2		T65	6		T66	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T114	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T115	1		T116	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T64	2		T65	4		T114	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T64	1		T65	3		T66	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T118	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T64	1		T65	1		T66	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T64	3		T65	3		T66	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T119	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T64	1		T115	1		T120	1