Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2654090

1

T2

77

T4

354

T7

55

full_word

1656169

1

T1

4

T2

10

T4

30

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4309969	1			T1	4		T2	87		T4	384
auto[TlIntgErrCmd]	83	1			T63	6		T64	2		T65	3
auto[TlIntgErrData]	92	1			T63	2		T64	3		T65	3
auto[TlIntgErrBoth]	115	1			T63	2		T64	5		T65	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

683974

1

T1

4

T2

87

T4

384

auto[1]

3626285

1

T11

96398

T12

334254

T13

113774

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	293304	1			T2	77		T4	354		T7	55
auto[TlIntgErrNone]	partial	auto[1]	2360523	1			T11	62391		T12	215453		T13	75403
auto[TlIntgErrNone]	full_word	auto[0]	390543	1			T1	4		T2	10		T4	30
auto[TlIntgErrNone]	full_word	auto[1]	1265599	1			T11	34007		T12	118801		T13	38371
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T63	2		T64	1		T135	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T63	4		T64	1		T65	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T132	1		T137	1		T138	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T130	1		T127	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T64	2		T65	1		T133	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T63	2		T64	1		T65	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T131	1		T139	1		T140	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T135	1		T127	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T63	1		T64	1		T65	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T63	1		T64	4		T65	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T130	1		T141	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T133	1		T130	1		T128	1