Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2900842

1

T1

159

T2

127

T3

200072

full_word

1872034

1

T1

25

T2

17

T3

137730

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4772566	1			T1	184		T2	144		T3	337802
auto[TlIntgErrCmd]	101	1			T51	2		T52	11		T53	7
auto[TlIntgErrData]	98	1			T51	2		T52	5		T53	5
auto[TlIntgErrBoth]	111	1			T51	6		T52	4		T53	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

762823

1

T1

184

T2

144

T3

52740

auto[1]

4010053

1

T3

285062

T11

462551

T12

85690

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	319929	1			T1	159		T2	127		T3	20160
auto[TlIntgErrNone]	partial	auto[1]	2580629	1			T3	179912		T11	298744		T12	55508
auto[TlIntgErrNone]	full_word	auto[0]	442761	1			T1	25		T2	17		T3	32580
auto[TlIntgErrNone]	full_word	auto[1]	1429247	1			T3	105150		T11	163807		T12	30182
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T52	4		T53	3		T106	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T51	2		T52	6		T53	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T111	1		T109	1		T110	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T52	1		T106	1		T111	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T51	2		T52	4		T53	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T52	1		T53	2		T106	4
auto[TlIntgErrData]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T53	1		T110	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T51	1		T52	1		T53	3
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T51	5		T52	1		T53	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T52	2		T106	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T108	1		T107	2		T115	1