Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1282120

1

T2

7

T3

24

T5

100021

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	358897	1			T2	55		T3	330		T5	26069
values[0x0]	483675	1			T5	37852		T20	79546		T21	32585
values[0x1]	501572	1			T5	39152		T20	82483		T21	33742

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31574	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1312570

1

T2

29

T3

204

T5

101392

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4953	1			T5	381		T11	1		T14	2
valid_sources[0x01]	4950	1			T3	2		T5	416		T8	2
valid_sources[0x02]	4806	1			T5	441		T14	2		T26	1
valid_sources[0x03]	5718	1			T5	400		T8	4		T14	1
valid_sources[0x04]	5123	1			T5	400		T11	1		T14	1
valid_sources[0x05]	4695	1			T5	415		T13	2		T60	2
valid_sources[0x06]	5014	1			T5	423		T11	2		T14	1
valid_sources[0x07]	6052	1			T5	371		T11	1		T59	3
valid_sources[0x08]	4896	1			T5	369		T11	1		T59	1
valid_sources[0x09]	5300	1			T5	410		T8	6		T59	1
valid_sources[0x0a]	5171	1			T5	400		T8	6		T11	1
valid_sources[0x0b]	4758	1			T5	361		T14	1		T59	2
valid_sources[0x0c]	4871	1			T5	447		T10	8		T59	1
valid_sources[0x0d]	4955	1			T3	4		T5	390		T11	2
valid_sources[0x0e]	5090	1			T5	414		T14	2		T59	3
valid_sources[0x0f]	4874	1			T5	413		T8	2		T59	1
valid_sources[0x10]	6054	1			T5	429		T8	4		T14	1
valid_sources[0x11]	5249	1			T5	415		T14	2		T127	5
valid_sources[0x12]	5031	1			T5	409		T8	9		T14	1
valid_sources[0x13]	4982	1			T5	415		T11	8		T14	1
valid_sources[0x14]	5583	1			T2	1		T5	413		T14	2
valid_sources[0x15]	5694	1			T5	399		T11	1		T14	2
valid_sources[0x16]	5878	1			T3	15		T5	404		T8	2
valid_sources[0x17]	5379	1			T5	393		T10	3		T11	2
valid_sources[0x18]	4834	1			T2	1		T3	1		T5	402
valid_sources[0x19]	5642	1			T2	2		T5	397		T14	1
valid_sources[0x1a]	4832	1			T2	2		T5	414		T8	4
valid_sources[0x1b]	5161	1			T5	416		T8	4		T11	1
valid_sources[0x1c]	5259	1			T2	1		T5	424		T8	6
valid_sources[0x1d]	5246	1			T2	2		T5	408		T6	1
valid_sources[0x1e]	5242	1			T5	417		T59	2		T60	1
valid_sources[0x1f]	7447	1			T2	1		T3	12		T5	401
valid_sources[0x20]	5060	1			T3	3		T5	378		T26	1
valid_sources[0x21]	5198	1			T5	414		T8	1		T11	2
valid_sources[0x22]	5086	1			T5	407		T60	2		T12	1
valid_sources[0x23]	4786	1			T5	391		T8	4		T11	1
valid_sources[0x24]	4897	1			T5	438		T26	1		T59	2
valid_sources[0x25]	5060	1			T5	421		T14	2		T59	6
valid_sources[0x26]	5160	1			T3	11		T5	423		T8	2
valid_sources[0x27]	5125	1			T5	392		T8	3		T14	2
valid_sources[0x28]	5837	1			T3	4		T5	392		T8	2
valid_sources[0x29]	4844	1			T5	368		T8	1		T10	1
valid_sources[0x2a]	5284	1			T5	358		T11	2		T59	1
valid_sources[0x2b]	4942	1			T5	405		T8	1		T14	1
valid_sources[0x2c]	5073	1			T5	384		T114	1		T20	847
valid_sources[0x2d]	5667	1			T5	390		T8	4		T14	1
valid_sources[0x2e]	6022	1			T5	413		T60	2		T127	1
valid_sources[0x2f]	4909	1			T2	1		T5	434		T8	2
valid_sources[0x30]	5376	1			T5	384		T73	2		T12	2
valid_sources[0x31]	5303	1			T5	408		T8	3		T59	3
valid_sources[0x32]	4981	1			T5	411		T8	2		T11	3
valid_sources[0x33]	4802	1			T2	1		T5	401		T8	4
valid_sources[0x34]	4803	1			T5	409		T11	2		T60	1
valid_sources[0x35]	5056	1			T5	379		T8	1		T59	2
valid_sources[0x36]	5190	1			T5	408		T8	2		T11	2
valid_sources[0x37]	6022	1			T3	2		T5	376		T11	2
valid_sources[0x38]	5162	1			T2	1		T5	363		T60	1
valid_sources[0x39]	5123	1			T3	4		T5	421		T14	4
valid_sources[0x3a]	4733	1			T5	404		T14	5		T20	824
valid_sources[0x3b]	5516	1			T5	409		T11	1		T60	2
valid_sources[0x3c]	5068	1			T2	1		T5	403		T8	1
valid_sources[0x3d]	5654	1			T3	8		T5	369		T8	2
valid_sources[0x3e]	5065	1			T5	410		T8	1		T11	6
valid_sources[0x3f]	4906	1			T5	405		T8	1		T60	6
valid_sources[0x40]	6090	1			T5	421		T8	4		T14	1
valid_sources[0x41]	5262	1			T2	1		T5	407		T11	1
valid_sources[0x42]	5001	1			T5	429		T8	2		T11	3
valid_sources[0x43]	4970	1			T5	426		T8	3		T14	2
valid_sources[0x44]	5381	1			T5	363		T8	7		T14	2
valid_sources[0x45]	4931	1			T5	359		T8	4		T11	1
valid_sources[0x46]	4852	1			T5	426		T11	1		T113	1
valid_sources[0x47]	5111	1			T5	378		T8	1		T14	1
valid_sources[0x48]	5589	1			T5	426		T10	2		T11	2
valid_sources[0x49]	5071	1			T2	1		T5	401		T8	1
valid_sources[0x4a]	5219	1			T3	13		T5	419		T11	1
valid_sources[0x4b]	5053	1			T2	1		T5	394		T8	2
valid_sources[0x4c]	6462	1			T5	435		T8	1		T11	1
valid_sources[0x4d]	4910	1			T5	406		T14	1		T73	1
valid_sources[0x4e]	4961	1			T5	395		T8	3		T14	3
valid_sources[0x4f]	4895	1			T5	404		T14	2		T59	1
valid_sources[0x50]	4898	1			T5	413		T59	1		T12	1
valid_sources[0x51]	5771	1			T5	440		T14	3		T12	2
valid_sources[0x52]	4944	1			T5	389		T60	1		T73	3
valid_sources[0x53]	5828	1			T5	409		T11	2		T14	5
valid_sources[0x54]	4912	1			T5	399		T8	6		T14	2
valid_sources[0x55]	4897	1			T5	435		T10	1		T11	2
valid_sources[0x56]	5153	1			T2	1		T5	397		T26	1
valid_sources[0x57]	5345	1			T5	401		T8	1		T11	2
valid_sources[0x58]	4863	1			T2	1		T5	417		T12	2
valid_sources[0x59]	4758	1			T5	389		T8	1		T11	1
valid_sources[0x5a]	5254	1			T5	405		T8	2		T14	4
valid_sources[0x5b]	5289	1			T5	442		T60	3		T114	5
valid_sources[0x5c]	5703	1			T5	398		T8	3		T14	1
valid_sources[0x5d]	5308	1			T5	459		T8	2		T14	2
valid_sources[0x5e]	5091	1			T5	394		T11	2		T14	3
valid_sources[0x5f]	5479	1			T3	11		T5	377		T8	2
valid_sources[0x60]	4841	1			T5	444		T8	3		T11	2
valid_sources[0x61]	5156	1			T5	416		T8	6		T11	1
valid_sources[0x62]	5495	1			T5	411		T10	2		T14	2
valid_sources[0x63]	5088	1			T2	1		T5	396		T6	1
valid_sources[0x64]	5304	1			T5	416		T8	2		T14	1
valid_sources[0x65]	5493	1			T5	394		T11	1		T14	3
valid_sources[0x66]	4896	1			T2	1		T3	11		T5	404
valid_sources[0x67]	6078	1			T5	386		T60	1		T12	1
valid_sources[0x68]	4825	1			T2	1		T5	411		T11	1
valid_sources[0x69]	5807	1			T5	432		T8	4		T14	2
valid_sources[0x6a]	5645	1			T5	409		T59	5		T60	1
valid_sources[0x6b]	4648	1			T5	377		T8	1		T14	1
valid_sources[0x6c]	5256	1			T5	407		T8	2		T14	1
valid_sources[0x6d]	5042	1			T3	4		T5	386		T11	1
valid_sources[0x6e]	6043	1			T5	412		T59	2		T60	1
valid_sources[0x6f]	5016	1			T3	25		T5	383		T10	2
valid_sources[0x70]	6114	1			T5	378		T8	3		T11	1
valid_sources[0x71]	4791	1			T3	27		T5	383		T8	2
valid_sources[0x72]	5038	1			T5	411		T8	1		T14	1
valid_sources[0x73]	4910	1			T3	13		T5	404		T8	4
valid_sources[0x74]	5299	1			T3	4		T5	391		T11	1
valid_sources[0x75]	4755	1			T5	382		T11	1		T14	1
valid_sources[0x76]	5073	1			T3	6		T5	374		T8	2
valid_sources[0x77]	5140	1			T5	415		T8	1		T14	4
valid_sources[0x78]	7045	1			T5	422		T8	6		T60	7
valid_sources[0x79]	4777	1			T2	1		T5	401		T8	2
valid_sources[0x7a]	4803	1			T2	1		T5	412		T8	1
valid_sources[0x7b]	4916	1			T5	369		T8	3		T11	1
valid_sources[0x7c]	4858	1			T3	9		T5	395		T8	3
valid_sources[0x7d]	5191	1			T5	379		T8	1		T14	2
valid_sources[0x7e]	4762	1			T2	1		T3	7		T5	383
valid_sources[0x7f]	5995	1			T5	422		T11	2		T59	1
valid_sources[0x80]	4764	1			T5	391		T8	3		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

323217

1

T2

7

T3

24

T5

25027

values[0x0]

all_enables

biggest_size

479302

1

T5

37520

T20

78803

T21

32285

values[0x1]

all_enables

biggest_size

479601

1

T5

37474

T20

78854

T21

32334

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	98459	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

988351

1

T1

1

T2

11

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	274470	1			T1	1		T2	32		T4	1
values[0x0]	376954	1			T5	28477		T7	11		T18	11
values[0x1]	435386	1			T5	32807		T7	3		T18	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1041482

1

T1

1

T2

16

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4071	1			T5	300		T20	670		T58	1
valid_sources[0x01]	3867	1			T5	306		T26	2		T20	668
valid_sources[0x02]	4307	1			T5	310		T10	1		T13	1
valid_sources[0x03]	4162	1			T5	339		T20	663		T21	276
valid_sources[0x04]	4165	1			T5	341		T20	709		T21	288
valid_sources[0x05]	4618	1			T5	288		T20	609		T128	1
valid_sources[0x06]	4299	1			T5	315		T20	641		T21	286
valid_sources[0x07]	4053	1			T5	309		T10	1		T38	1
valid_sources[0x08]	4173	1			T5	290		T113	1		T20	667
valid_sources[0x09]	4488	1			T5	313		T18	1		T59	3
valid_sources[0x0a]	3962	1			T5	321		T13	1		T51	2
valid_sources[0x0b]	4423	1			T5	245		T9	1		T113	1
valid_sources[0x0c]	4257	1			T5	304		T18	1		T20	712
valid_sources[0x0d]	3967	1			T5	289		T51	3		T73	1
valid_sources[0x0e]	4673	1			T5	305		T20	683		T128	1
valid_sources[0x0f]	3830	1			T5	324		T20	658		T21	310
valid_sources[0x10]	4471	1			T5	312		T63	6		T20	752
valid_sources[0x11]	4534	1			T5	330		T20	704		T21	216
valid_sources[0x12]	4541	1			T5	339		T20	729		T21	283
valid_sources[0x13]	4224	1			T5	296		T11	10		T129	1
valid_sources[0x14]	4909	1			T5	333		T18	1		T20	728
valid_sources[0x15]	4602	1			T5	299		T6	4		T10	1
valid_sources[0x16]	4724	1			T5	293		T10	2		T13	1
valid_sources[0x17]	4166	1			T5	297		T73	1		T20	663
valid_sources[0x18]	4854	1			T5	333		T113	2		T20	673
valid_sources[0x19]	4093	1			T5	296		T10	1		T51	1
valid_sources[0x1a]	4687	1			T5	354		T19	5		T20	757
valid_sources[0x1b]	4415	1			T5	316		T20	684		T21	250
valid_sources[0x1c]	4117	1			T5	269		T20	686		T128	1
valid_sources[0x1d]	4426	1			T5	309		T55	9		T113	1
valid_sources[0x1e]	4169	1			T5	285		T20	660		T21	310
valid_sources[0x1f]	4011	1			T5	287		T20	676		T21	282
valid_sources[0x20]	4132	1			T5	300		T113	1		T20	741
valid_sources[0x21]	4450	1			T5	296		T73	3		T20	671
valid_sources[0x22]	4320	1			T5	300		T26	1		T20	711
valid_sources[0x23]	4152	1			T5	352		T29	4		T20	653
valid_sources[0x24]	4295	1			T5	335		T73	1		T20	670
valid_sources[0x25]	3929	1			T5	346		T6	4		T20	668
valid_sources[0x26]	4322	1			T5	301		T13	2		T130	4
valid_sources[0x27]	4291	1			T5	330		T18	1		T20	692
valid_sources[0x28]	4703	1			T5	330		T6	4		T10	1
valid_sources[0x29]	4544	1			T5	312		T59	7		T20	705
valid_sources[0x2a]	3922	1			T5	286		T20	658		T30	6
valid_sources[0x2b]	4315	1			T5	323		T13	1		T20	683
valid_sources[0x2c]	4648	1			T5	308		T20	697		T21	304
valid_sources[0x2d]	4099	1			T5	301		T18	1		T20	678
valid_sources[0x2e]	4359	1			T5	330		T20	694		T30	1
valid_sources[0x2f]	4406	1			T5	328		T20	678		T21	291
valid_sources[0x30]	4410	1			T5	364		T59	10		T20	665
valid_sources[0x31]	4395	1			T5	339		T73	1		T20	728
valid_sources[0x32]	4453	1			T5	324		T113	1		T73	1
valid_sources[0x33]	4554	1			T5	324		T20	705		T128	1
valid_sources[0x34]	4189	1			T5	358		T56	2		T20	663
valid_sources[0x35]	4021	1			T5	314		T59	9		T20	647
valid_sources[0x36]	4490	1			T5	303		T13	1		T20	651
valid_sources[0x37]	4107	1			T5	352		T51	1		T20	675
valid_sources[0x38]	4153	1			T5	325		T13	1		T56	1
valid_sources[0x39]	4332	1			T5	377		T10	2		T59	2
valid_sources[0x3a]	4662	1			T5	298		T11	2		T20	675
valid_sources[0x3b]	4082	1			T5	301		T59	5		T20	682
valid_sources[0x3c]	4037	1			T5	315		T20	665		T30	5
valid_sources[0x3d]	4360	1			T5	328		T73	1		T20	707
valid_sources[0x3e]	4301	1			T5	338		T20	657		T21	330
valid_sources[0x3f]	4258	1			T5	316		T20	681		T128	1
valid_sources[0x40]	4171	1			T5	330		T13	1		T20	653
valid_sources[0x41]	4356	1			T5	330		T9	1		T20	634
valid_sources[0x42]	4239	1			T5	287		T6	3		T51	3
valid_sources[0x43]	3779	1			T5	324		T20	670		T21	252
valid_sources[0x44]	3944	1			T5	331		T18	1		T29	4
valid_sources[0x45]	4518	1			T5	300		T20	663		T128	1
valid_sources[0x46]	4068	1			T5	358		T10	1		T20	720
valid_sources[0x47]	3895	1			T5	327		T20	659		T21	279
valid_sources[0x48]	4038	1			T5	300		T20	682		T128	1
valid_sources[0x49]	4700	1			T5	291		T10	4		T20	694
valid_sources[0x4a]	4211	1			T5	334		T26	1		T20	641
valid_sources[0x4b]	3992	1			T5	314		T113	1		T20	627
valid_sources[0x4c]	4098	1			T5	313		T59	1		T20	665
valid_sources[0x4d]	3899	1			T5	317		T20	716		T21	243
valid_sources[0x4e]	4342	1			T5	330		T20	705		T21	296
valid_sources[0x4f]	4420	1			T5	300		T20	689		T21	290
valid_sources[0x50]	4382	1			T5	299		T9	1		T13	1
valid_sources[0x51]	4206	1			T5	279		T13	1		T20	669
valid_sources[0x52]	4764	1			T5	373		T13	1		T20	655
valid_sources[0x53]	4107	1			T5	346		T15	4		T20	660
valid_sources[0x54]	4452	1			T5	340		T20	666		T21	264
valid_sources[0x55]	4229	1			T5	315		T13	1		T20	728
valid_sources[0x56]	4176	1			T1	1		T5	282		T13	1
valid_sources[0x57]	3970	1			T5	346		T51	2		T20	682
valid_sources[0x58]	3946	1			T5	342		T13	1		T20	618
valid_sources[0x59]	4011	1			T5	314		T10	1		T51	6
valid_sources[0x5a]	4323	1			T5	303		T29	8		T20	683
valid_sources[0x5b]	4200	1			T5	352		T27	14		T59	2
valid_sources[0x5c]	4460	1			T5	363		T9	1		T51	1
valid_sources[0x5d]	3969	1			T5	306		T59	1		T61	1
valid_sources[0x5e]	3983	1			T5	361		T20	682		T21	284
valid_sources[0x5f]	4110	1			T5	328		T113	1		T56	1
valid_sources[0x60]	3767	1			T5	283		T73	1		T20	624
valid_sources[0x61]	3767	1			T5	306		T51	3		T12	64
valid_sources[0x62]	4162	1			T5	325		T20	711		T21	306
valid_sources[0x63]	4753	1			T5	342		T20	677		T21	264
valid_sources[0x64]	4554	1			T5	309		T10	1		T20	715
valid_sources[0x65]	4288	1			T5	329		T20	689		T21	304
valid_sources[0x66]	4240	1			T5	327		T20	706		T128	1
valid_sources[0x67]	3932	1			T5	327		T20	664		T128	1
valid_sources[0x68]	4118	1			T5	337		T6	1		T13	1
valid_sources[0x69]	4155	1			T5	310		T20	658		T75	1
valid_sources[0x6a]	4719	1			T5	325		T13	1		T20	696
valid_sources[0x6b]	4171	1			T5	313		T73	2		T20	625
valid_sources[0x6c]	4352	1			T5	344		T9	2		T59	25
valid_sources[0x6d]	4109	1			T5	325		T113	1		T20	651
valid_sources[0x6e]	4290	1			T5	285		T9	1		T20	664
valid_sources[0x6f]	4490	1			T5	294		T113	2		T20	676
valid_sources[0x70]	4175	1			T5	330		T20	680		T30	4
valid_sources[0x71]	4324	1			T5	288		T20	630		T21	308
valid_sources[0x72]	4472	1			T5	326		T59	2		T20	676
valid_sources[0x73]	4682	1			T5	343		T18	1		T20	703
valid_sources[0x74]	4266	1			T5	338		T56	1		T20	694
valid_sources[0x75]	4308	1			T5	291		T59	13		T131	1
valid_sources[0x76]	4216	1			T5	311		T20	686		T21	278
valid_sources[0x77]	4076	1			T5	321		T113	1		T20	686
valid_sources[0x78]	3981	1			T5	328		T20	686		T132	3
valid_sources[0x79]	4176	1			T5	322		T10	2		T20	661
valid_sources[0x7a]	4498	1			T5	315		T51	1		T20	660
valid_sources[0x7b]	4482	1			T5	325		T20	716		T21	224
valid_sources[0x7c]	4405	1			T5	336		T15	1		T20	680
valid_sources[0x7d]	3793	1			T5	345		T10	1		T113	2
valid_sources[0x7e]	4352	1			T5	318		T20	662		T21	288
valid_sources[0x7f]	4450	1			T5	317		T20	654		T21	337
valid_sources[0x80]	4192	1			T5	348		T73	1		T20	670

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

250829

1

T1

1

T2

11

T4

1

values[0x0]

all_enables

biggest_size

368988

1

T5

27926

T7

5

T18

3

values[0x1]

all_enables

biggest_size

368534

1

T5

28022

T25

1

T56

1