Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2352377

1

T2

48

T3

306

T5

177642

full_word

1495984

1

T2

7

T3

24

T5

116480

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3848111	1			T2	55		T3	330		T5	294122
auto[TlIntgErrCmd]	72	1			T48	2		T49	4		T50	4
auto[TlIntgErrData]	82	1			T48	2		T49	2		T50	1
auto[TlIntgErrBoth]	96	1			T48	6		T49	4		T50	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618559

1

T2

55

T3

330

T5

45846

auto[1]

3229802

1

T5

248276

T20

536558

T21

219421

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	264391	1			T2	48		T3	306		T5	18439
auto[TlIntgErrNone]	partial	auto[1]	2087764	1			T5	159203		T20	348343		T21	142377
auto[TlIntgErrNone]	full_word	auto[0]	354052	1			T2	7		T3	24		T5	27407
auto[TlIntgErrNone]	full_word	auto[1]	1141904	1			T5	89073		T20	188215		T21	77044
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T48	2		T49	3		T50	1
auto[TlIntgErrCmd]	partial	auto[1]	31	1			T50	2		T117	2		T122	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T49	1		T117	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T50	1		T122	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T48	2		T49	2		T117	5
auto[TlIntgErrData]	partial	auto[1]	34	1			T117	1		T124	1		T125	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T122	1		T125	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T50	1		T122	1		T125	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T48	4		T49	1		T50	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T48	2		T49	3		T50	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T117	1		T118	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T118	1		T126	1		T123	1