Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3719727

1

T2

241926

T4

120

T5

287

full_word

2341289

1

T2

154543

T3

2

T4

14

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6060726	1			T2	396469		T3	2		T4	134
auto[TlIntgErrCmd]	96	1			T52	2		T53	3		T54	5
auto[TlIntgErrData]	101	1			T52	3		T53	2		T54	2
auto[TlIntgErrBoth]	93	1			T52	5		T53	5		T54	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

955893

1

T2

61228

T3

2

T4

134

auto[1]

5105123

1

T2

335241

T11

136846

T20

289375

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	403276	1			T2	24892		T4	120		T5	287
auto[TlIntgErrNone]	partial	auto[1]	3316191	1			T2	217034		T11	91569		T20	185991
auto[TlIntgErrNone]	full_word	auto[0]	552487	1			T2	36336		T3	2		T4	14
auto[TlIntgErrNone]	full_word	auto[1]	1788772	1			T2	118207		T11	45277		T20	103384
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T53	2		T54	1		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T53	1		T54	4		T119	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T115	1		T123	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T52	2		T119	1		T116	2
auto[TlIntgErrData]	partial	auto[0]	49	1			T53	1		T119	1		T116	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T52	2		T53	1		T54	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T119	1		T116	1		T123	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T52	1		T54	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T52	3		T53	4		T54	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T52	1		T53	1		T54	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T123	1		T118	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T52	1		T119	1		T116	1