Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

924283

1

T3

7

T4

6

T6

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	263803	1			T3	114		T4	6		T6	309
values[0x0]	348940	1			T19	36985		T20	25508		T21	19802
values[0x1]	360740	1			T19	38350		T20	26326		T21	20707

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24433	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

949050

1

T3

61

T4

6

T6

193

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3477	1			T3	1		T6	1		T10	4
valid_sources[0x01]	4088	1			T26	1		T114	66		T40	2
valid_sources[0x02]	4024	1			T26	2		T48	1		T15	3
valid_sources[0x03]	3632	1			T3	2		T6	14		T8	10
valid_sources[0x04]	3407	1			T8	3		T13	1		T40	1
valid_sources[0x05]	3755	1			T10	3		T40	2		T15	2
valid_sources[0x06]	5045	1			T3	1		T11	1		T23	1
valid_sources[0x07]	3093	1			T3	1		T11	1		T26	1
valid_sources[0x08]	3278	1			T11	1		T40	1		T15	2
valid_sources[0x09]	3107	1			T11	1		T48	8		T13	1
valid_sources[0x0a]	4554	1			T10	3		T22	2		T48	1
valid_sources[0x0b]	5362	1			T8	15		T26	1		T13	2
valid_sources[0x0c]	3429	1			T3	1		T6	8		T10	1
valid_sources[0x0d]	3203	1			T10	10		T23	1		T15	1
valid_sources[0x0e]	3904	1			T10	1		T11	1		T48	1
valid_sources[0x0f]	3390	1			T3	3		T6	7		T11	1
valid_sources[0x10]	3354	1			T8	2		T10	1		T11	1
valid_sources[0x11]	3554	1			T8	1		T10	8		T23	17
valid_sources[0x12]	3650	1			T6	3		T8	2		T11	1
valid_sources[0x13]	2992	1			T8	2		T127	3		T128	2
valid_sources[0x14]	3891	1			T22	3		T48	1		T15	2
valid_sources[0x15]	3812	1			T11	1		T26	2		T24	2
valid_sources[0x16]	3466	1			T6	5		T8	4		T9	24
valid_sources[0x17]	2982	1			T3	1		T6	11		T10	8
valid_sources[0x18]	3745	1			T23	4		T48	1		T40	1
valid_sources[0x19]	3216	1			T8	14		T113	1		T40	1
valid_sources[0x1a]	3508	1			T11	1		T22	1		T114	22
valid_sources[0x1b]	3485	1			T10	3		T26	1		T40	2
valid_sources[0x1c]	4469	1			T10	6		T15	1		T19	386
valid_sources[0x1d]	4457	1			T10	5		T11	2		T40	1
valid_sources[0x1e]	4445	1			T10	2		T42	1		T129	1
valid_sources[0x1f]	3502	1			T8	4		T24	2		T40	1
valid_sources[0x20]	5328	1			T3	1		T6	7		T10	6
valid_sources[0x21]	5100	1			T8	1		T48	1		T15	4
valid_sources[0x22]	3890	1			T10	4		T24	1		T40	1
valid_sources[0x23]	3782	1			T6	11		T10	7		T48	1
valid_sources[0x24]	4034	1			T48	5		T40	4		T15	1
valid_sources[0x25]	3559	1			T8	2		T10	2		T48	1
valid_sources[0x26]	3842	1			T8	12		T22	1		T26	1
valid_sources[0x27]	3563	1			T8	5		T22	1		T48	6
valid_sources[0x28]	3797	1			T113	6		T24	4		T15	1
valid_sources[0x29]	3785	1			T6	7		T11	1		T48	2
valid_sources[0x2a]	3519	1			T10	2		T48	1		T113	2
valid_sources[0x2b]	3198	1			T3	1		T10	1		T129	2
valid_sources[0x2c]	3318	1			T10	6		T11	1		T22	1
valid_sources[0x2d]	4462	1			T11	2		T13	3		T24	1
valid_sources[0x2e]	3622	1			T10	1		T11	1		T13	1
valid_sources[0x2f]	4203	1			T3	1		T24	1		T42	8
valid_sources[0x30]	3719	1			T11	1		T26	1		T24	1
valid_sources[0x31]	3632	1			T9	29		T22	2		T26	1
valid_sources[0x32]	4736	1			T11	1		T22	1		T15	2
valid_sources[0x33]	3161	1			T3	2		T10	1		T23	2
valid_sources[0x34]	3649	1			T3	1		T8	1		T10	1
valid_sources[0x35]	3234	1			T3	2		T10	2		T11	1
valid_sources[0x36]	3638	1			T3	2		T11	1		T24	1
valid_sources[0x37]	4699	1			T48	5		T40	1		T15	2
valid_sources[0x38]	3540	1			T6	4		T10	1		T27	1
valid_sources[0x39]	4019	1			T6	1		T10	1		T26	1
valid_sources[0x3a]	3979	1			T3	1		T10	3		T24	1
valid_sources[0x3b]	4970	1			T3	2		T10	1		T48	5
valid_sources[0x3c]	3167	1			T40	1		T19	362		T20	242
valid_sources[0x3d]	3732	1			T40	2		T42	2		T129	1
valid_sources[0x3e]	5218	1			T3	1		T10	2		T26	1
valid_sources[0x3f]	3554	1			T8	2		T26	2		T48	3
valid_sources[0x40]	3617	1			T3	3		T10	3		T26	1
valid_sources[0x41]	2896	1			T8	2		T11	1		T24	1
valid_sources[0x42]	3408	1			T10	2		T11	2		T24	1
valid_sources[0x43]	3732	1			T10	3		T11	2		T48	2
valid_sources[0x44]	2893	1			T3	1		T10	10		T48	1
valid_sources[0x45]	3731	1			T11	1		T26	1		T13	2
valid_sources[0x46]	3615	1			T3	1		T13	2		T24	3
valid_sources[0x47]	3428	1			T6	10		T8	1		T48	6
valid_sources[0x48]	3809	1			T10	1		T40	1		T15	1
valid_sources[0x49]	3291	1			T23	8		T24	2		T40	2
valid_sources[0x4a]	3521	1			T8	4		T13	1		T24	3
valid_sources[0x4b]	2991	1			T6	20		T8	25		T26	1
valid_sources[0x4c]	2836	1			T23	25		T40	1		T129	1
valid_sources[0x4d]	3909	1			T3	4		T11	3		T26	1
valid_sources[0x4e]	3649	1			T48	3		T130	3		T98	3
valid_sources[0x4f]	4333	1			T23	1		T15	1		T128	1
valid_sources[0x50]	4107	1			T10	1		T26	1		T15	1
valid_sources[0x51]	4380	1			T10	3		T40	1		T15	2
valid_sources[0x52]	3398	1			T3	1		T6	3		T48	2
valid_sources[0x53]	3089	1			T10	4		T11	1		T48	1
valid_sources[0x54]	3880	1			T10	1		T26	1		T48	3
valid_sources[0x55]	3862	1			T11	2		T128	4		T19	401
valid_sources[0x56]	4259	1			T10	4		T26	1		T23	5
valid_sources[0x57]	4296	1			T10	2		T23	13		T40	2
valid_sources[0x58]	3214	1			T8	18		T10	1		T48	1
valid_sources[0x59]	4089	1			T26	1		T27	1		T24	3
valid_sources[0x5a]	3726	1			T8	2		T10	2		T48	2
valid_sources[0x5b]	3088	1			T3	2		T8	2		T26	3
valid_sources[0x5c]	5276	1			T11	2		T48	6		T40	1
valid_sources[0x5d]	4467	1			T10	2		T48	7		T13	2
valid_sources[0x5e]	3927	1			T8	19		T10	1		T23	8
valid_sources[0x5f]	3538	1			T3	1		T10	2		T40	2
valid_sources[0x60]	4221	1			T10	1		T26	1		T13	1
valid_sources[0x61]	4571	1			T48	1		T40	1		T128	3
valid_sources[0x62]	4348	1			T11	1		T26	1		T48	5
valid_sources[0x63]	3629	1			T3	1		T6	22		T8	2
valid_sources[0x64]	3585	1			T3	1		T24	2		T40	1
valid_sources[0x65]	3056	1			T48	4		T19	399		T20	254
valid_sources[0x66]	4011	1			T10	1		T26	1		T40	4
valid_sources[0x67]	3591	1			T3	1		T8	13		T10	15
valid_sources[0x68]	3198	1			T6	8		T10	5		T11	1
valid_sources[0x69]	3928	1			T8	18		T10	1		T11	1
valid_sources[0x6a]	3536	1			T3	1		T8	1		T26	1
valid_sources[0x6b]	4337	1			T26	1		T40	2		T130	5
valid_sources[0x6c]	3255	1			T3	1		T10	1		T11	1
valid_sources[0x6d]	2790	1			T15	6		T19	382		T65	1
valid_sources[0x6e]	3342	1			T3	1		T11	1		T48	1
valid_sources[0x6f]	3198	1			T22	5		T40	2		T15	1
valid_sources[0x70]	3665	1			T26	1		T48	3		T24	3
valid_sources[0x71]	3207	1			T8	7		T10	1		T11	1
valid_sources[0x72]	5065	1			T3	1		T6	3		T10	2
valid_sources[0x73]	4073	1			T3	2		T48	2		T113	3
valid_sources[0x74]	5290	1			T3	2		T11	3		T26	1
valid_sources[0x75]	3225	1			T8	16		T10	3		T11	1
valid_sources[0x76]	3941	1			T6	7		T10	4		T48	3
valid_sources[0x77]	3413	1			T3	1		T8	5		T48	2
valid_sources[0x78]	4203	1			T4	6		T10	10		T11	1
valid_sources[0x79]	3025	1			T3	1		T6	6		T11	3
valid_sources[0x7a]	3979	1			T11	1		T113	6		T15	2
valid_sources[0x7b]	3337	1			T10	1		T22	1		T24	3
valid_sources[0x7c]	4175	1			T3	1		T8	6		T10	3
valid_sources[0x7d]	2944	1			T8	6		T22	2		T48	6
valid_sources[0x7e]	4236	1			T3	2		T10	1		T11	1
valid_sources[0x7f]	3339	1			T10	10		T11	2		T24	1
valid_sources[0x80]	3869	1			T3	2		T8	1		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

233702

1

T3

7

T4

6

T6

27

values[0x0]

all_enables

biggest_size

345818

1

T19

36645

T20

25267

T21

19653

values[0x1]

all_enables

biggest_size

344763

1

T19

36610

T20

25150

T21

19841

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

712929

1

T1

1

T4

9

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	200182	1			T2	1		T4	14		T8	192
values[0x0]	271496	1			T1	2		T5	11		T7	2
values[0x1]	315880	1			T1	1		T5	4		T32	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

752575

1

T1

1

T4

11

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3435	1			T44	1		T24	73		T42	1
valid_sources[0x01]	3577	1			T8	1		T40	2		T42	1
valid_sources[0x02]	3111	1			T23	1		T42	2		T19	300
valid_sources[0x03]	2815	1			T23	1		T42	1		T19	294
valid_sources[0x04]	3140	1			T44	1		T43	2		T19	348
valid_sources[0x05]	2897	1			T19	332		T20	242		T131	2
valid_sources[0x06]	3017	1			T29	1		T42	1		T127	5
valid_sources[0x07]	3013	1			T8	2		T40	1		T42	3
valid_sources[0x08]	2919	1			T8	1		T14	1		T84	2
valid_sources[0x09]	3127	1			T8	2		T44	1		T42	1
valid_sources[0x0a]	2683	1			T8	1		T23	1		T42	1
valid_sources[0x0b]	3716	1			T8	1		T23	1		T127	1
valid_sources[0x0c]	2944	1			T19	300		T20	226		T132	1
valid_sources[0x0d]	2904	1			T11	1		T19	294		T20	222
valid_sources[0x0e]	2881	1			T8	1		T27	1		T23	1
valid_sources[0x0f]	3386	1			T5	1		T23	1		T74	18
valid_sources[0x10]	3130	1			T8	2		T84	2		T127	1
valid_sources[0x11]	3002	1			T8	2		T40	1		T42	1
valid_sources[0x12]	3191	1			T85	2		T19	352		T20	276
valid_sources[0x13]	2996	1			T28	5		T42	2		T19	306
valid_sources[0x14]	3370	1			T113	2		T19	329		T63	2
valid_sources[0x15]	2940	1			T4	14		T8	2		T47	4
valid_sources[0x16]	2955	1			T127	2		T100	2		T19	313
valid_sources[0x17]	3072	1			T8	2		T23	1		T42	1
valid_sources[0x18]	3537	1			T19	274		T20	205		T133	1
valid_sources[0x19]	3238	1			T8	1		T100	2		T19	312
valid_sources[0x1a]	3572	1			T8	2		T23	1		T16	1
valid_sources[0x1b]	3022	1			T5	1		T84	1		T19	340
valid_sources[0x1c]	2876	1			T42	2		T19	280		T20	202
valid_sources[0x1d]	3105	1			T29	1		T42	1		T100	1
valid_sources[0x1e]	3130	1			T99	1		T19	308		T20	235
valid_sources[0x1f]	3325	1			T23	1		T100	2		T19	275
valid_sources[0x20]	2879	1			T34	1		T84	1		T19	323
valid_sources[0x21]	3032	1			T8	2		T23	1		T19	314
valid_sources[0x22]	3193	1			T8	1		T23	2		T129	32
valid_sources[0x23]	3552	1			T29	2		T19	319		T20	189
valid_sources[0x24]	2945	1			T19	318		T20	209		T133	3
valid_sources[0x25]	3049	1			T8	1		T40	7		T19	295
valid_sources[0x26]	3271	1			T8	1		T127	1		T19	328
valid_sources[0x27]	2912	1			T19	290		T20	190		T132	1
valid_sources[0x28]	3089	1			T8	2		T44	1		T84	3
valid_sources[0x29]	3179	1			T8	1		T27	2		T100	1
valid_sources[0x2a]	3389	1			T1	3		T5	1		T42	2
valid_sources[0x2b]	2876	1			T23	1		T100	3		T19	334
valid_sources[0x2c]	2904	1			T8	1		T44	1		T42	1
valid_sources[0x2d]	3166	1			T23	1		T19	261		T20	232
valid_sources[0x2e]	3197	1			T11	1		T84	1		T85	1
valid_sources[0x2f]	3308	1			T8	1		T23	2		T42	3
valid_sources[0x30]	2836	1			T39	1		T19	332		T20	179
valid_sources[0x31]	2844	1			T8	2		T40	2		T42	1
valid_sources[0x32]	2796	1			T8	1		T40	4		T41	2
valid_sources[0x33]	3221	1			T44	2		T12	12		T40	1
valid_sources[0x34]	2907	1			T11	15		T23	1		T19	302
valid_sources[0x35]	3406	1			T22	9		T42	3		T19	332
valid_sources[0x36]	3756	1			T40	3		T16	2		T100	1
valid_sources[0x37]	3081	1			T23	1		T19	330		T20	198
valid_sources[0x38]	2991	1			T8	3		T22	8		T101	1
valid_sources[0x39]	3399	1			T23	1		T19	298		T20	213
valid_sources[0x3a]	2937	1			T23	1		T42	1		T85	3
valid_sources[0x3b]	2988	1			T42	1		T19	333		T20	201
valid_sources[0x3c]	2974	1			T2	1		T42	1		T19	309
valid_sources[0x3d]	3013	1			T8	2		T23	1		T25	34
valid_sources[0x3e]	2990	1			T8	1		T40	1		T19	330
valid_sources[0x3f]	2956	1			T127	1		T19	332		T20	244
valid_sources[0x40]	2965	1			T40	1		T127	3		T19	326
valid_sources[0x41]	2902	1			T8	2		T33	1		T42	2
valid_sources[0x42]	2955	1			T8	4		T44	1		T42	2
valid_sources[0x43]	2985	1			T8	1		T42	1		T85	1
valid_sources[0x44]	2787	1			T8	3		T42	1		T127	1
valid_sources[0x45]	2819	1			T8	7		T41	1		T99	1
valid_sources[0x46]	2949	1			T113	2		T14	2		T100	1
valid_sources[0x47]	3703	1			T17	1		T42	3		T100	1
valid_sources[0x48]	3208	1			T40	3		T42	1		T85	1
valid_sources[0x49]	3113	1			T5	1		T8	2		T29	1
valid_sources[0x4a]	3300	1			T42	1		T19	326		T20	228
valid_sources[0x4b]	2824	1			T27	1		T42	1		T43	1
valid_sources[0x4c]	2998	1			T14	2		T84	2		T100	2
valid_sources[0x4d]	2807	1			T8	1		T16	3		T50	1
valid_sources[0x4e]	3027	1			T5	1		T23	2		T100	1
valid_sources[0x4f]	2998	1			T8	4		T28	5		T42	1
valid_sources[0x50]	3146	1			T5	1		T19	306		T20	232
valid_sources[0x51]	2883	1			T23	1		T42	1		T16	4
valid_sources[0x52]	3190	1			T22	9		T27	1		T23	1
valid_sources[0x53]	4130	1			T8	3		T45	2		T127	4
valid_sources[0x54]	2850	1			T8	1		T18	13		T45	1
valid_sources[0x55]	2923	1			T8	4		T45	3		T42	1
valid_sources[0x56]	2946	1			T19	354		T20	187		T134	1
valid_sources[0x57]	2990	1			T32	1		T42	1		T100	3
valid_sources[0x58]	3485	1			T42	1		T19	289		T20	251
valid_sources[0x59]	2834	1			T27	1		T19	302		T20	223
valid_sources[0x5a]	2857	1			T40	1		T84	2		T100	3
valid_sources[0x5b]	3027	1			T8	2		T23	1		T19	305
valid_sources[0x5c]	2911	1			T28	6		T23	1		T40	1
valid_sources[0x5d]	2870	1			T28	10		T100	1		T19	322
valid_sources[0x5e]	2965	1			T8	1		T16	3		T19	306
valid_sources[0x5f]	2988	1			T8	1		T27	2		T23	1
valid_sources[0x60]	3029	1			T85	1		T19	313		T20	215
valid_sources[0x61]	3287	1			T8	4		T42	2		T19	368
valid_sources[0x62]	2821	1			T8	1		T23	2		T43	6
valid_sources[0x63]	2970	1			T8	3		T19	362		T20	219
valid_sources[0x64]	3020	1			T8	1		T11	5		T28	4
valid_sources[0x65]	2996	1			T41	3		T19	303		T20	182
valid_sources[0x66]	3247	1			T8	2		T42	2		T100	2
valid_sources[0x67]	3219	1			T8	1		T27	1		T99	1
valid_sources[0x68]	3235	1			T100	3		T19	295		T60	1
valid_sources[0x69]	2895	1			T42	1		T100	3		T19	332
valid_sources[0x6a]	3458	1			T5	1		T41	1		T42	1
valid_sources[0x6b]	2928	1			T27	2		T29	1		T85	1
valid_sources[0x6c]	2639	1			T8	1		T42	3		T43	1
valid_sources[0x6d]	2941	1			T5	1		T8	1		T22	1
valid_sources[0x6e]	3096	1			T40	3		T42	1		T19	289
valid_sources[0x6f]	2946	1			T8	1		T23	1		T45	7
valid_sources[0x70]	2906	1			T8	2		T29	1		T40	5
valid_sources[0x71]	2875	1			T8	1		T84	1		T100	2
valid_sources[0x72]	2713	1			T19	328		T20	210		T135	1
valid_sources[0x73]	2861	1			T19	315		T20	210		T135	2
valid_sources[0x74]	2900	1			T23	1		T84	3		T99	1
valid_sources[0x75]	3091	1			T8	3		T42	2		T85	1
valid_sources[0x76]	2899	1			T5	1		T100	1		T19	350
valid_sources[0x77]	2798	1			T100	1		T19	288		T60	1
valid_sources[0x78]	3200	1			T44	1		T100	1		T19	315
valid_sources[0x79]	3335	1			T8	2		T23	1		T127	1
valid_sources[0x7a]	2981	1			T8	1		T42	1		T43	1
valid_sources[0x7b]	2953	1			T23	1		T42	1		T99	1
valid_sources[0x7c]	3048	1			T40	2		T42	1		T128	96
valid_sources[0x7d]	3544	1			T8	2		T127	2		T85	1
valid_sources[0x7e]	3082	1			T19	294		T20	208		T136	7
valid_sources[0x7f]	2939	1			T8	1		T44	1		T19	301
valid_sources[0x80]	3265	1			T43	3		T19	322		T20	227

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

181170

1

T4

9

T8

86

T11

24

values[0x0]

all_enables

biggest_size

265553

1

T1

1

T5

1

T47

1

values[0x1]

all_enables

biggest_size

266206

1

T12

1

T18

1

T74

2