Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
1711015 |
1 |
|
|
T3 |
107 |
|
T6 |
282 |
|
T8 |
360 |
full_word |
1080162 |
1 |
|
|
T3 |
7 |
|
T4 |
4 |
|
T6 |
27 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
2790847 |
1 |
|
|
T3 |
114 |
|
T4 |
4 |
|
T6 |
309 |
auto[TlIntgErrCmd] |
101 |
1 |
|
|
T68 |
6 |
|
T69 |
7 |
|
T70 |
4 |
auto[TlIntgErrData] |
127 |
1 |
|
|
T68 |
8 |
|
T69 |
8 |
|
T70 |
3 |
auto[TlIntgErrBoth] |
102 |
1 |
|
|
T68 |
6 |
|
T69 |
5 |
|
T70 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
453876 |
1 |
|
|
T3 |
114 |
|
T4 |
4 |
|
T6 |
309 |
auto[1] |
2337301 |
1 |
|
|
T19 |
249786 |
|
T20 |
167105 |
|
T21 |
129296 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
197399 |
1 |
|
|
T3 |
107 |
|
T6 |
282 |
|
T8 |
360 |
auto[TlIntgErrNone] |
partial |
auto[1] |
1513323 |
1 |
|
|
T19 |
162284 |
|
T20 |
107348 |
|
T21 |
82396 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
256332 |
1 |
|
|
T3 |
7 |
|
T4 |
4 |
|
T6 |
27 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
823793 |
1 |
|
|
T19 |
87502 |
|
T20 |
59757 |
|
T21 |
46900 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
38 |
1 |
|
|
T69 |
2 |
|
T70 |
1 |
|
T117 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
52 |
1 |
|
|
T68 |
5 |
|
T69 |
3 |
|
T70 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
6 |
1 |
|
|
T68 |
1 |
|
T119 |
1 |
|
T121 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
5 |
1 |
|
|
T69 |
2 |
|
T116 |
1 |
|
T122 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
54 |
1 |
|
|
T68 |
1 |
|
T69 |
6 |
|
T70 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
58 |
1 |
|
|
T68 |
6 |
|
T69 |
1 |
|
T70 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
4 |
1 |
|
|
T68 |
1 |
|
T69 |
1 |
|
T122 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
11 |
1 |
|
|
T70 |
1 |
|
T122 |
2 |
|
T123 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
39 |
1 |
|
|
T68 |
1 |
|
T69 |
2 |
|
T70 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
52 |
1 |
|
|
T68 |
5 |
|
T69 |
3 |
|
T70 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
4 |
1 |
|
|
T122 |
2 |
|
T121 |
1 |
|
T124 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
7 |
1 |
|
|
T123 |
2 |
|
T125 |
1 |
|
T126 |
2 |