Unified Coverage Report :: Group :: cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	92.86	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_errors_cgs_wrap[rom_ctrl_prim_reg_block]	85.71	1	100	1	64	64
tl_errors_cgs_wrap[rom_ctrl_regs_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_errors_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance tl_errors_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	5	10	85.71

Variables for Group Instance tl_errors_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_csr_size_err	2	1	1	50.00	100	0	0	2
cp_instr_type_err	2	0	2	100.00	100	1	1	2
cp_mem_byte_access_err	2	1	1	50.00	100	0	0	2
cp_mem_ro_err	2	0	2	100.00	100	1	1	2
cp_mem_wo_err	2	1	1	50.00	100	0	0	2
cp_tl_protocol_err	1	0	1	100.00	100	1	1	0
cp_unmapped_err	2	1	1	50.00	100	0	0	2
cp_write_w_instr_type_err	2	1	1	50.00	100	1	1	2

---

Group Instance : tl_errors_cgs_wrap[rom_ctrl_regs_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_errors_cgs_wrap[rom_ctrl_regs_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	3	12	100.00

Variables for Group Instance tl_errors_cgs_wrap[rom_ctrl_regs_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_csr_size_err	2	0	2	100.00	100	1	1	2
cp_instr_type_err	2	0	2	100.00	100	1	1	2
cp_mem_byte_access_err	2	1	1	50.00	100	0	0	2
cp_mem_ro_err	2	1	1	50.00	100	0	0	2
cp_mem_wo_err	2	1	1	50.00	100	0	0	2
cp_tl_protocol_err	1	0	1	100.00	100	1	1	0
cp_unmapped_err	2	0	2	100.00	100	1	1	2
cp_write_w_instr_type_err	2	0	2	100.00	100	1	1	2

Summary for Variable cp_csr_size_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_csr_size_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	616019	0			T5	144328		T11	57001		T12	34940

---

Summary for Variable cp_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_instr_type_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

287810

1

T5

68089

T11

26547

T12

16606

auto[1]

328209

1

T5

76239

T11

30454

T12

18334

---

Summary for Variable cp_mem_byte_access_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_byte_access_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	616019	0			T5	144328		T11	57001		T12	34940

---

Summary for Variable cp_mem_ro_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_ro_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

588387

1

T5

137941

T11

54315

T12

33368

auto[1]

27632

1

T5

6387

T11

2686

T12

1572

---

Summary for Variable cp_mem_wo_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_wo_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	616019	0			T5	144328		T11	57001		T12	34940

---

Summary for Variable cp_tl_protocol_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_tl_protocol_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

covered

260088

1

T5

61702

T11

23861

T12

15034

---

Summary for Variable cp_unmapped_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_unmapped_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	616019	0			T5	144328		T11	57001		T12	34940

---

Summary for Variable cp_write_w_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_write_w_instr_type_err

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616019

1

T5

144328

T11

57001

T12

34940

Summary for Variable cp_csr_size_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_csr_size_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

905424

1

T5

209776

T11

84778

T12

51620

auto[1]

57765

1

T5

12948

T11

5281

T12

3520

---

Summary for Variable cp_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_instr_type_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687761

1

T5

159403

T11

63932

T12

39615

auto[1]

275428

1

T5

63321

T11

26127

T12

15525

---

Summary for Variable cp_mem_byte_access_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_byte_access_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	963189	0			T5	222724		T11	90059		T12	55140

---

Summary for Variable cp_mem_ro_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_ro_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	963189	0			T5	222724		T11	90059		T12	55140

---

Summary for Variable cp_mem_wo_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_wo_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	963189	0			T5	222724		T11	90059		T12	55140

---

Summary for Variable cp_tl_protocol_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_tl_protocol_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

covered

322960

1

T5

75784

T11

29922

T12

18563

---

Summary for Variable cp_unmapped_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unmapped_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931200

1

T5

215340

T11

86944

T12

53139

auto[1]

31989

1

T5

7384

T11

3115

T12

2001

---

Summary for Variable cp_write_w_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write_w_instr_type_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

688203

1

T5

159437

T11

64445

T12

39609

auto[1]

274986

1

T5

63287

T11

25614

T12

15531