Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1316699

1

T1

2

T2

10

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	364998	1			T1	56		T2	171		T4	66
values[0x0]	496473	1			T5	114897		T11	46012		T12	27709
values[0x1]	514533	1			T5	119585		T11	47590		T12	28946

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30094	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1345910

1

T1

35

T2

111

T4

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5445	1			T5	1240		T8	1		T10	9
valid_sources[0x01]	5700	1			T5	1520		T9	1		T11	547
valid_sources[0x02]	4387	1			T5	416		T11	466		T47	1
valid_sources[0x03]	6200	1			T5	1818		T6	1		T11	498
valid_sources[0x04]	5525	1			T5	1339		T11	459		T46	30
valid_sources[0x05]	5064	1			T5	1139		T6	2		T9	1
valid_sources[0x06]	5309	1			T5	1292		T8	1		T11	491
valid_sources[0x07]	5076	1			T5	1030		T6	1		T9	1
valid_sources[0x08]	7519	1			T5	3461		T6	4		T11	512
valid_sources[0x09]	5191	1			T5	708		T6	1		T9	2
valid_sources[0x0a]	5163	1			T2	22		T4	2		T5	1304
valid_sources[0x0b]	4316	1			T5	112		T6	1		T11	472
valid_sources[0x0c]	4805	1			T5	876		T11	466		T47	5
valid_sources[0x0d]	5823	1			T5	1271		T16	2		T11	514
valid_sources[0x0e]	5132	1			T1	7		T4	1		T5	1217
valid_sources[0x0f]	6074	1			T4	1		T5	2199		T8	1
valid_sources[0x10]	5502	1			T5	1501		T8	1		T11	489
valid_sources[0x11]	5865	1			T5	1801		T11	477		T12	288
valid_sources[0x12]	5494	1			T5	606		T6	2		T11	539
valid_sources[0x13]	4492	1			T1	3		T5	568		T8	1
valid_sources[0x14]	4457	1			T5	536		T11	491		T12	290
valid_sources[0x15]	5058	1			T5	1135		T6	1		T10	6
valid_sources[0x16]	4923	1			T5	982		T8	1		T11	504
valid_sources[0x17]	5696	1			T5	1603		T11	516		T76	1
valid_sources[0x18]	5124	1			T5	1138		T6	1		T16	1
valid_sources[0x19]	5626	1			T5	1760		T10	2		T18	3
valid_sources[0x1a]	7509	1			T5	2081		T6	2		T11	522
valid_sources[0x1b]	4800	1			T2	19		T5	853		T6	2
valid_sources[0x1c]	6079	1			T5	1977		T6	1		T8	1
valid_sources[0x1d]	5376	1			T2	87		T5	722		T9	4
valid_sources[0x1e]	6753	1			T5	2359		T6	2		T11	473
valid_sources[0x1f]	4624	1			T5	339		T11	495		T47	5
valid_sources[0x20]	5124	1			T5	1039		T11	506		T17	2
valid_sources[0x21]	4679	1			T4	1		T5	694		T8	1
valid_sources[0x22]	4800	1			T5	797		T8	1		T16	1
valid_sources[0x23]	5181	1			T1	4		T5	1328		T8	1
valid_sources[0x24]	5323	1			T5	1326		T11	432		T47	4
valid_sources[0x25]	5081	1			T5	833		T16	2		T11	518
valid_sources[0x26]	5294	1			T5	1197		T8	2		T11	519
valid_sources[0x27]	5436	1			T4	2		T5	1419		T6	1
valid_sources[0x28]	5342	1			T4	2		T5	1221		T6	1
valid_sources[0x29]	4824	1			T5	686		T11	453		T47	2
valid_sources[0x2a]	4723	1			T4	2		T5	418		T6	1
valid_sources[0x2b]	5136	1			T5	1078		T11	499		T47	1
valid_sources[0x2c]	5671	1			T5	1759		T8	1		T11	484
valid_sources[0x2d]	5236	1			T1	1		T5	834		T9	4
valid_sources[0x2e]	5248	1			T5	919		T15	33		T11	473
valid_sources[0x2f]	4611	1			T5	500		T6	1		T11	477
valid_sources[0x30]	7183	1			T5	2799		T9	2		T16	2
valid_sources[0x31]	7038	1			T4	1		T5	2584		T9	1
valid_sources[0x32]	5071	1			T1	1		T5	1018		T8	2
valid_sources[0x33]	4248	1			T5	283		T11	536		T47	1
valid_sources[0x34]	4839	1			T5	981		T11	492		T47	9
valid_sources[0x35]	5280	1			T5	797		T16	2		T11	459
valid_sources[0x36]	4940	1			T5	767		T6	1		T11	511
valid_sources[0x37]	4464	1			T5	385		T6	1		T8	1
valid_sources[0x38]	6589	1			T5	2440		T11	487		T14	2
valid_sources[0x39]	5688	1			T4	1		T5	1411		T8	1
valid_sources[0x3a]	5159	1			T5	1107		T6	1		T11	537
valid_sources[0x3b]	5819	1			T5	1838		T6	1		T11	509
valid_sources[0x3c]	5218	1			T5	1145		T9	2		T15	14
valid_sources[0x3d]	5715	1			T5	1561		T11	511		T47	1
valid_sources[0x3e]	4857	1			T5	894		T11	517		T12	275
valid_sources[0x3f]	5535	1			T5	1477		T11	485		T47	7
valid_sources[0x40]	6070	1			T5	1818		T8	1		T9	3
valid_sources[0x41]	5726	1			T5	1724		T8	1		T18	3
valid_sources[0x42]	5945	1			T5	1313		T9	5		T11	494
valid_sources[0x43]	5101	1			T5	1169		T8	1		T9	2
valid_sources[0x44]	4972	1			T5	1111		T9	3		T11	467
valid_sources[0x45]	4551	1			T5	468		T16	2		T11	519
valid_sources[0x46]	5477	1			T4	3		T5	786		T11	478
valid_sources[0x47]	4190	1			T5	222		T6	1		T11	499
valid_sources[0x48]	4379	1			T5	492		T9	4		T11	489
valid_sources[0x49]	5742	1			T1	1		T5	1402		T6	2
valid_sources[0x4a]	5054	1			T5	1072		T6	2		T16	1
valid_sources[0x4b]	6138	1			T5	2184		T6	1		T11	535
valid_sources[0x4c]	5062	1			T5	1053		T11	530		T14	1
valid_sources[0x4d]	5261	1			T5	1346		T8	1		T16	1
valid_sources[0x4e]	5247	1			T5	1291		T9	2		T11	485
valid_sources[0x4f]	5384	1			T1	3		T5	861		T6	3
valid_sources[0x50]	4988	1			T5	1000		T11	512		T47	5
valid_sources[0x51]	5381	1			T5	590		T9	1		T16	1
valid_sources[0x52]	5556	1			T5	1568		T9	1		T11	449
valid_sources[0x53]	4742	1			T5	816		T11	471		T47	1
valid_sources[0x54]	5172	1			T5	1206		T8	1		T16	1
valid_sources[0x55]	6588	1			T5	2553		T11	491		T76	3
valid_sources[0x56]	5272	1			T5	672		T6	2		T11	558
valid_sources[0x57]	4967	1			T4	4		T5	1046		T6	1
valid_sources[0x58]	5426	1			T5	1554		T11	466		T47	2
valid_sources[0x59]	5901	1			T5	1369		T6	1		T11	465
valid_sources[0x5a]	5320	1			T1	1		T5	968		T11	479
valid_sources[0x5b]	4991	1			T5	750		T8	1		T11	505
valid_sources[0x5c]	5362	1			T4	2		T5	1409		T8	1
valid_sources[0x5d]	6087	1			T5	2139		T11	500		T47	2
valid_sources[0x5e]	4568	1			T4	2		T5	574		T8	2
valid_sources[0x5f]	5670	1			T5	1689		T11	516		T12	288
valid_sources[0x60]	4806	1			T5	964		T9	3		T11	463
valid_sources[0x61]	4673	1			T4	2		T5	664		T6	2
valid_sources[0x62]	5178	1			T5	1337		T11	505		T47	1
valid_sources[0x63]	5050	1			T1	1		T5	1135		T6	1
valid_sources[0x64]	6458	1			T1	1		T5	2585		T11	461
valid_sources[0x65]	5613	1			T5	1541		T6	1		T11	545
valid_sources[0x66]	5973	1			T5	1248		T9	2		T11	477
valid_sources[0x67]	4208	1			T5	144		T8	1		T11	476
valid_sources[0x68]	5953	1			T5	999		T8	3		T11	501
valid_sources[0x69]	5841	1			T5	1188		T8	1		T11	537
valid_sources[0x6a]	5235	1			T5	1150		T6	1		T16	1
valid_sources[0x6b]	5423	1			T1	2		T5	1407		T11	500
valid_sources[0x6c]	5479	1			T5	712		T8	1		T11	473
valid_sources[0x6d]	5421	1			T4	2		T5	1448		T6	1
valid_sources[0x6e]	5726	1			T1	1		T5	752		T6	1
valid_sources[0x6f]	5208	1			T5	858		T8	3		T11	472
valid_sources[0x70]	5671	1			T5	1390		T11	465		T14	1
valid_sources[0x71]	4241	1			T1	2		T5	278		T6	1
valid_sources[0x72]	5439	1			T5	1417		T16	2		T11	499
valid_sources[0x73]	4573	1			T5	688		T9	6		T11	460
valid_sources[0x74]	4596	1			T1	2		T5	195		T8	1
valid_sources[0x75]	5165	1			T5	1320		T8	1		T11	463
valid_sources[0x76]	6934	1			T1	1		T5	2392		T6	1
valid_sources[0x77]	4084	1			T5	159		T11	449		T12	310
valid_sources[0x78]	5458	1			T5	1416		T11	482		T47	1
valid_sources[0x79]	5349	1			T4	1		T5	1281		T9	1
valid_sources[0x7a]	7426	1			T1	1		T4	1		T5	3552
valid_sources[0x7b]	5173	1			T5	1367		T6	1		T11	473
valid_sources[0x7c]	5260	1			T1	2		T5	1285		T8	1
valid_sources[0x7d]	5292	1			T2	21		T5	1134		T11	490
valid_sources[0x7e]	6761	1			T5	2611		T11	453		T12	288
valid_sources[0x7f]	6830	1			T5	2638		T11	507		T12	260
valid_sources[0x80]	5878	1			T5	1494		T9	2		T11	512

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

331964

1

T1

2

T2

10

T4

4

values[0x0]

all_enables

biggest_size

492143

1

T5

113873

T11

45596

T12

27471

values[0x1]

all_enables

biggest_size

492592

1

T5

114561

T11

45449

T12

27684

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	99183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

997921

1

T2

28

T4

10

T5

224841

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	275669	1			T2	64		T4	32		T5	59828
values[0x0]	380410	1			T5	85788		T11	35262		T23	6
values[0x1]	441025	1			T3	4		T5	99532		T11	40742

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45070	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1052034

1

T2

37

T3

1

T4

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4479	1			T5	1009		T11	435		T76	1
valid_sources[0x01]	3908	1			T4	1		T5	931		T8	1
valid_sources[0x02]	4383	1			T4	2		T5	898		T11	346
valid_sources[0x03]	4636	1			T5	954		T11	343		T12	199
valid_sources[0x04]	3942	1			T5	985		T8	1		T11	436
valid_sources[0x05]	4508	1			T5	925		T11	367		T76	1
valid_sources[0x06]	4332	1			T5	968		T11	376		T12	206
valid_sources[0x07]	4061	1			T5	992		T11	402		T12	170
valid_sources[0x08]	4083	1			T5	976		T11	429		T24	3
valid_sources[0x09]	4131	1			T5	927		T8	1		T11	382
valid_sources[0x0a]	4489	1			T5	1048		T11	396		T12	184
valid_sources[0x0b]	4339	1			T5	1000		T11	387		T14	1
valid_sources[0x0c]	4913	1			T5	851		T18	8		T11	392
valid_sources[0x0d]	4777	1			T2	64		T5	935		T11	405
valid_sources[0x0e]	4288	1			T5	900		T6	1		T11	334
valid_sources[0x0f]	4253	1			T5	906		T11	354		T23	1
valid_sources[0x10]	4094	1			T3	1		T5	916		T11	315
valid_sources[0x11]	3947	1			T4	2		T5	969		T11	423
valid_sources[0x12]	4183	1			T4	1		T5	970		T15	3
valid_sources[0x13]	4767	1			T5	1040		T11	396		T17	1
valid_sources[0x14]	3700	1			T5	1006		T11	392		T17	1
valid_sources[0x15]	4027	1			T5	999		T6	2		T11	435
valid_sources[0x16]	4192	1			T5	975		T11	448		T17	1
valid_sources[0x17]	4092	1			T5	1009		T11	416		T12	207
valid_sources[0x18]	5083	1			T5	1027		T16	5		T11	403
valid_sources[0x19]	3976	1			T5	841		T11	399		T76	1
valid_sources[0x1a]	4987	1			T5	929		T11	409		T12	260
valid_sources[0x1b]	4767	1			T5	1056		T6	2		T8	1
valid_sources[0x1c]	3971	1			T5	890		T18	2		T11	403
valid_sources[0x1d]	4412	1			T5	1016		T11	378		T12	267
valid_sources[0x1e]	4060	1			T5	893		T15	3		T11	405
valid_sources[0x1f]	4222	1			T5	948		T11	337		T12	283
valid_sources[0x20]	4095	1			T5	944		T10	32		T11	427
valid_sources[0x21]	4207	1			T5	908		T11	418		T12	217
valid_sources[0x22]	3925	1			T5	934		T11	388		T76	2
valid_sources[0x23]	4114	1			T5	965		T15	5		T11	343
valid_sources[0x24]	3936	1			T5	1006		T11	404		T12	202
valid_sources[0x25]	4231	1			T5	956		T6	1		T11	387
valid_sources[0x26]	4808	1			T5	1015		T11	416		T12	291
valid_sources[0x27]	4028	1			T4	1		T5	964		T11	400
valid_sources[0x28]	4237	1			T4	1		T5	927		T18	1
valid_sources[0x29]	4404	1			T5	1041		T11	390		T76	1
valid_sources[0x2a]	4058	1			T5	1010		T11	350		T12	310
valid_sources[0x2b]	3995	1			T5	875		T11	428		T12	298
valid_sources[0x2c]	4160	1			T5	950		T11	357		T76	1
valid_sources[0x2d]	4411	1			T5	909		T6	1		T8	1
valid_sources[0x2e]	4072	1			T5	967		T11	406		T76	1
valid_sources[0x2f]	4268	1			T5	931		T6	1		T11	409
valid_sources[0x30]	4185	1			T5	905		T11	458		T12	223
valid_sources[0x31]	4252	1			T5	966		T18	3		T11	383
valid_sources[0x32]	3857	1			T5	918		T18	1		T11	386
valid_sources[0x33]	4242	1			T5	987		T6	3		T11	416
valid_sources[0x34]	4266	1			T5	929		T11	412		T12	230
valid_sources[0x35]	4312	1			T5	955		T6	1		T11	398
valid_sources[0x36]	4042	1			T5	884		T11	401		T17	1
valid_sources[0x37]	4349	1			T5	1039		T11	415		T23	1
valid_sources[0x38]	4386	1			T5	923		T8	1		T11	395
valid_sources[0x39]	3747	1			T5	938		T11	400		T76	1
valid_sources[0x3a]	4504	1			T5	951		T6	2		T11	436
valid_sources[0x3b]	4610	1			T5	1003		T11	433		T12	238
valid_sources[0x3c]	4424	1			T5	919		T7	1		T11	411
valid_sources[0x3d]	4518	1			T4	10		T5	994		T11	410
valid_sources[0x3e]	4468	1			T5	943		T11	393		T12	306
valid_sources[0x3f]	4030	1			T5	855		T8	2		T16	3
valid_sources[0x40]	4678	1			T5	919		T11	369		T12	223
valid_sources[0x41]	3978	1			T5	937		T6	1		T11	404
valid_sources[0x42]	4588	1			T5	1013		T11	404		T12	248
valid_sources[0x43]	4283	1			T5	969		T8	1		T11	457
valid_sources[0x44]	4369	1			T5	972		T11	440		T76	1
valid_sources[0x45]	4042	1			T5	1027		T6	1		T11	439
valid_sources[0x46]	3904	1			T5	889		T11	450		T12	253
valid_sources[0x47]	4077	1			T5	944		T11	472		T17	1
valid_sources[0x48]	4345	1			T5	956		T6	1		T11	438
valid_sources[0x49]	4362	1			T5	917		T11	390		T12	217
valid_sources[0x4a]	3953	1			T5	934		T11	367		T12	184
valid_sources[0x4b]	3781	1			T5	846		T11	402		T76	1
valid_sources[0x4c]	3852	1			T5	899		T11	385		T23	1
valid_sources[0x4d]	3848	1			T5	1003		T11	398		T76	2
valid_sources[0x4e]	4428	1			T5	941		T11	396		T76	1
valid_sources[0x4f]	4382	1			T5	1019		T11	371		T17	1
valid_sources[0x50]	4534	1			T5	917		T11	376		T14	2
valid_sources[0x51]	4307	1			T5	878		T11	368		T23	1
valid_sources[0x52]	3926	1			T5	1015		T11	361		T12	277
valid_sources[0x53]	4566	1			T5	1024		T11	432		T12	292
valid_sources[0x54]	4632	1			T5	948		T11	381		T76	1
valid_sources[0x55]	4232	1			T5	911		T11	410		T12	302
valid_sources[0x56]	4602	1			T3	2		T5	948		T11	371
valid_sources[0x57]	4086	1			T5	898		T8	1		T11	414
valid_sources[0x58]	4052	1			T5	989		T6	2		T11	355
valid_sources[0x59]	3722	1			T5	880		T8	2		T11	361
valid_sources[0x5a]	4040	1			T5	886		T6	1		T11	366
valid_sources[0x5b]	4772	1			T5	950		T11	388		T12	199
valid_sources[0x5c]	4175	1			T5	1101		T11	391		T14	1
valid_sources[0x5d]	4257	1			T5	1008		T11	465		T14	1
valid_sources[0x5e]	4347	1			T5	962		T18	2		T11	389
valid_sources[0x5f]	3991	1			T5	981		T16	1		T11	318
valid_sources[0x60]	4233	1			T5	891		T11	401		T12	204
valid_sources[0x61]	4359	1			T5	982		T8	1		T11	441
valid_sources[0x62]	4421	1			T5	973		T11	392		T12	260
valid_sources[0x63]	4046	1			T5	996		T8	1		T11	424
valid_sources[0x64]	4316	1			T5	1045		T11	344		T17	1
valid_sources[0x65]	4361	1			T5	956		T8	1		T18	4
valid_sources[0x66]	4634	1			T5	890		T11	398		T12	300
valid_sources[0x67]	4480	1			T5	1010		T15	1		T11	413
valid_sources[0x68]	4370	1			T5	953		T11	343		T12	257
valid_sources[0x69]	4348	1			T5	976		T11	432		T12	227
valid_sources[0x6a]	4019	1			T5	969		T11	412		T12	218
valid_sources[0x6b]	4213	1			T5	910		T11	379		T17	1
valid_sources[0x6c]	4573	1			T5	974		T11	360		T17	1
valid_sources[0x6d]	4184	1			T5	927		T11	421		T12	212
valid_sources[0x6e]	4194	1			T5	938		T11	339		T12	273
valid_sources[0x6f]	3921	1			T5	848		T15	3		T11	384
valid_sources[0x70]	4166	1			T5	1010		T11	390		T17	1
valid_sources[0x71]	4705	1			T5	976		T8	1		T11	416
valid_sources[0x72]	4352	1			T5	864		T11	414		T14	1
valid_sources[0x73]	3959	1			T5	1004		T11	441		T76	1
valid_sources[0x74]	4521	1			T5	1014		T11	408		T12	233
valid_sources[0x75]	3967	1			T5	950		T11	406		T12	232
valid_sources[0x76]	4473	1			T5	939		T11	410		T12	232
valid_sources[0x77]	5663	1			T5	1038		T11	415		T17	1
valid_sources[0x78]	4229	1			T5	924		T16	3		T11	373
valid_sources[0x79]	4631	1			T5	964		T11	376		T12	253
valid_sources[0x7a]	4372	1			T5	1014		T11	394		T12	262
valid_sources[0x7b]	4108	1			T5	1038		T6	1		T11	383
valid_sources[0x7c]	4438	1			T5	1163		T11	407		T17	1
valid_sources[0x7d]	4636	1			T4	1		T5	938		T11	354
valid_sources[0x7e]	4035	1			T5	982		T11	385		T12	225
valid_sources[0x7f]	4443	1			T5	982		T15	2		T16	4
valid_sources[0x80]	4100	1			T5	946		T11	374		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

252656

1

T2

28

T4

10

T5

56312

values[0x0]

all_enables

biggest_size

372409

1

T5

84163

T11

34583

T23

2

values[0x1]

all_enables

biggest_size

372856

1

T5

84366

T11

34524

T24

1