Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2359276

1

T1

54

T2

161

T4

62

full_word

1531869

1

T1

2

T2

10

T4

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3890865	1			T1	56		T2	171		T4	66
auto[TlIntgErrCmd]	85	1			T63	3		T64	5		T109	7
auto[TlIntgErrData]	95	1			T62	3		T63	2		T64	3
auto[TlIntgErrBoth]	100	1			T62	7		T63	5		T64	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

624993

1

T1

56

T2

171

T4

66

auto[1]

3266152

1

T5

757197

T11

303561

T12

186014

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	261732	1			T1	54		T2	161		T4	62
auto[TlIntgErrNone]	partial	auto[1]	2097288	1			T5	485776		T11	195578		T12	120438
auto[TlIntgErrNone]	full_word	auto[0]	363139	1			T1	2		T2	10		T4	4
auto[TlIntgErrNone]	full_word	auto[1]	1168706	1			T5	271421		T11	107983		T12	65576
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T63	3		T64	1		T109	4
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T64	4		T109	3		T110	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T110	1		T112	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T107	1		T108	1		T113	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T62	1		T63	1		T64	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T62	2		T63	1		T64	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T109	1		T114	2		T115	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T116	1		T117	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T62	5		T63	3		T109	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T62	2		T63	2		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T109	1		T116	1		T105	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T114	1		T117	1		T108	1