Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2214007

1

T1

185952

T2

50

T3

220

full_word

1411772

1

T1

115940

T2

1

T3

27

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3625459	1			T1	301892		T2	51		T3	247
auto[TlIntgErrCmd]	119	1			T63	5		T64	9		T65	4
auto[TlIntgErrData]	92	1			T63	7		T64	7		T65	3
auto[TlIntgErrBoth]	109	1			T63	8		T64	4		T65	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

580639

1

T1

46232

T2

51

T3

247

auto[1]

3045140

1

T1

255660

T13

63502

T14

811015

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	246995	1			T1	18972		T2	50		T3	220
auto[TlIntgErrNone]	partial	auto[1]	1966727	1			T1	166980		T13	40616		T14	526980
auto[TlIntgErrNone]	full_word	auto[0]	333497	1			T1	27260		T2	1		T3	27
auto[TlIntgErrNone]	full_word	auto[1]	1078240	1			T1	88680		T13	22886		T14	284035
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T63	2		T64	4		T65	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T63	2		T64	5		T65	2
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T63	1		T107	2		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T105	1		T114	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T63	1		T64	5		T65	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T63	5		T64	2		T65	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T105	2		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T63	1		T65	1		T105	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T63	2		T64	1		T65	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T63	5		T64	2		T65	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T116	1		T106	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T63	1		T64	1		T109	2