Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2829565

1

T1

185

T2

76

T7

70

full_word

1797553

1

T1

13

T2

3

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4626868	1			T1	198		T2	79		T4	2
auto[TlIntgErrCmd]	85	1			T50	6		T51	4		T52	4
auto[TlIntgErrData]	85	1			T50	8		T51	4		T52	5
auto[TlIntgErrBoth]	80	1			T50	6		T51	2		T52	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

732718

1

T1

198

T2

79

T4

2

auto[1]

3894400

1

T19

201254

T20

170577

T21

85158

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	307980	1			T1	185		T2	76		T7	70
auto[TlIntgErrNone]	partial	auto[1]	2521358	1			T19	129587		T20	113112		T21	54584
auto[TlIntgErrNone]	full_word	auto[0]	424627	1			T1	13		T2	3		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	1372903	1			T19	71667		T20	57465		T21	30574
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T50	4		T52	2		T91	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T50	2		T51	3		T52	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T51	1		T98	1		T99	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T52	1		T92	1		T100	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T50	3		T51	3		T52	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T50	4		T51	1		T52	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T50	1		T101	1		T102	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T100	1		T94	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	27	1			T50	2		T52	4		T91	2
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T50	2		T51	2		T52	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T50	2		T92	3		T93	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T52	1		T103	1		T104	1