Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4060479

1

T5

74

T7

35649

T8

179

full_word

2603340

1

T1

8

T4

8

T5

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6663499	1			T1	8		T4	8		T5	79
auto[TlIntgErrCmd]	95	1			T56	4		T57	5		T58	2
auto[TlIntgErrData]	117	1			T56	2		T57	3		T58	4
auto[TlIntgErrBoth]	108	1			T56	4		T57	2		T58	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051507

1

T1

8

T4

8

T5

79

auto[1]

5612312

1

T7

48046

T23

81016

T24

581948

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	436336	1			T5	74		T7	3833		T8	179
auto[TlIntgErrNone]	partial	auto[1]	3623855	1			T7	31816		T23	52606		T24	376676
auto[TlIntgErrNone]	full_word	auto[0]	615040	1			T1	8		T4	8		T5	5
auto[TlIntgErrNone]	full_word	auto[1]	1988268	1			T7	16230		T23	28410		T24	205272
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T56	1		T57	1		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T56	1		T57	4		T58	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T56	1		T124	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T56	1		T116	1		T120	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T56	1		T57	3		T58	1
auto[TlIntgErrData]	partial	auto[1]	57	1			T56	1		T58	3		T116	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T120	2		T124	2		T127	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T117	2		T121	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T56	2		T57	1		T58	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T56	2		T57	1		T58	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T128	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T117	1		T119	1		T123	1