Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2720987

1

T6

131

T8

116

T9

87

full_word

1744932

1

T2

6

T4

4

T5

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4465649	1			T2	6		T4	4		T5	8
auto[TlIntgErrCmd]	91	1			T44	7		T45	4		T46	11
auto[TlIntgErrData]	89	1			T44	9		T45	9		T46	6
auto[TlIntgErrBoth]	90	1			T44	4		T45	7		T46	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

716494

1

T2

6

T4

4

T5

8

auto[1]

3749425

1

T12

318629

T13

86890

T14

241715

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	303437	1			T6	131		T8	116		T9	87
auto[TlIntgErrNone]	partial	auto[1]	2417305	1			T12	205288		T13	55571		T14	156790
auto[TlIntgErrNone]	full_word	auto[0]	412925	1			T2	6		T4	4		T5	8
auto[TlIntgErrNone]	full_word	auto[1]	1331982	1			T12	113341		T13	31319		T14	84925
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T44	1		T45	2		T46	4
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T44	6		T45	2		T46	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T46	1		T97	1		T98	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T98	1		T99	1		T100	2
auto[TlIntgErrData]	partial	auto[0]	45	1			T44	4		T45	3		T46	4
auto[TlIntgErrData]	partial	auto[1]	32	1			T44	4		T45	3		T46	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T44	1		T45	2		T100	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T45	1		T101	1		T102	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T44	3		T45	3		T46	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T44	1		T45	4		T46	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T103	2		T104	1		-	-