Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48319	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

865321

1

T1

11

T2

5

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	248828	1			T1	143		T2	42		T3	57
values[0x0]	326041	1			T12	19034		T13	7740		T14	10962
values[0x1]	338771	1			T12	19765		T13	7896		T14	11518

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

889776

1

T1

78

T2

28

T3

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3451	1			T3	1		T6	1		T9	4
valid_sources[0x01]	3542	1			T3	1		T6	2		T9	3
valid_sources[0x02]	3344	1			T1	2		T9	4		T35	6
valid_sources[0x03]	3639	1			T6	1		T9	5		T11	1
valid_sources[0x04]	3498	1			T6	1		T9	4		T35	1
valid_sources[0x05]	3467	1			T6	2		T11	2		T35	1
valid_sources[0x06]	3608	1			T1	2		T4	2		T9	1
valid_sources[0x07]	3561	1			T4	1		T6	3		T11	2
valid_sources[0x08]	3364	1			T11	1		T35	2		T12	209
valid_sources[0x09]	3532	1			T11	2		T35	1		T12	200
valid_sources[0x0a]	3729	1			T3	1		T12	214		T105	1
valid_sources[0x0b]	3573	1			T4	3		T9	2		T11	1
valid_sources[0x0c]	3327	1			T7	3		T11	1		T35	1
valid_sources[0x0d]	3531	1			T2	10		T3	1		T4	2
valid_sources[0x0e]	3561	1			T7	1		T11	1		T35	1
valid_sources[0x0f]	3536	1			T4	1		T7	1		T12	196
valid_sources[0x10]	3679	1			T6	2		T9	2		T11	2
valid_sources[0x11]	3643	1			T6	1		T9	1		T12	205
valid_sources[0x12]	3333	1			T6	1		T11	2		T35	2
valid_sources[0x13]	3512	1			T6	1		T11	1		T12	191
valid_sources[0x14]	3596	1			T11	2		T35	5		T12	233
valid_sources[0x15]	3541	1			T3	1		T6	1		T9	4
valid_sources[0x16]	3448	1			T4	1		T6	3		T35	3
valid_sources[0x17]	3531	1			T6	2		T7	3		T9	6
valid_sources[0x18]	3810	1			T6	1		T11	2		T35	1
valid_sources[0x19]	3702	1			T1	1		T4	1		T11	1
valid_sources[0x1a]	3740	1			T4	1		T11	1		T35	2
valid_sources[0x1b]	3457	1			T6	3		T11	1		T35	1
valid_sources[0x1c]	3463	1			T6	1		T7	6		T9	12
valid_sources[0x1d]	3784	1			T3	1		T4	1		T6	1
valid_sources[0x1e]	3489	1			T1	10		T7	2		T11	2
valid_sources[0x1f]	3662	1			T6	2		T12	226		T104	2
valid_sources[0x20]	3536	1			T5	1		T35	1		T12	222
valid_sources[0x21]	3482	1			T3	4		T6	1		T9	1
valid_sources[0x22]	3551	1			T1	11		T4	2		T6	1
valid_sources[0x23]	3471	1			T4	2		T6	1		T7	1
valid_sources[0x24]	3510	1			T6	1		T9	4		T11	2
valid_sources[0x25]	3487	1			T3	1		T5	3		T6	1
valid_sources[0x26]	3564	1			T1	3		T6	2		T35	2
valid_sources[0x27]	3518	1			T5	21		T6	1		T35	1
valid_sources[0x28]	3437	1			T1	4		T6	2		T12	193
valid_sources[0x29]	3609	1			T6	1		T11	2		T35	2
valid_sources[0x2a]	3550	1			T6	2		T9	3		T12	209
valid_sources[0x2b]	3563	1			T35	1		T12	193		T31	1
valid_sources[0x2c]	3542	1			T12	203		T29	1		T119	5
valid_sources[0x2d]	3487	1			T4	1		T6	1		T9	4
valid_sources[0x2e]	3573	1			T6	1		T12	174		T13	103
valid_sources[0x2f]	3662	1			T1	2		T3	1		T35	3
valid_sources[0x30]	3437	1			T6	1		T35	2		T12	235
valid_sources[0x31]	3568	1			T6	3		T11	1		T35	3
valid_sources[0x32]	3746	1			T4	1		T6	1		T11	1
valid_sources[0x33]	3715	1			T4	1		T6	3		T9	1
valid_sources[0x34]	3473	1			T6	1		T11	1		T35	4
valid_sources[0x35]	3554	1			T3	2		T6	1		T35	1
valid_sources[0x36]	3498	1			T3	1		T12	171		T31	1
valid_sources[0x37]	3438	1			T3	1		T6	2		T11	3
valid_sources[0x38]	3647	1			T9	5		T12	219		T29	1
valid_sources[0x39]	3687	1			T4	1		T9	2		T35	1
valid_sources[0x3a]	3322	1			T12	176		T31	1		T119	1
valid_sources[0x3b]	3544	1			T1	32		T4	1		T6	1
valid_sources[0x3c]	3540	1			T9	4		T12	222		T29	1
valid_sources[0x3d]	3488	1			T9	6		T11	1		T12	193
valid_sources[0x3e]	3588	1			T1	4		T3	2		T4	2
valid_sources[0x3f]	3504	1			T6	1		T9	9		T35	3
valid_sources[0x40]	3531	1			T4	2		T11	2		T12	180
valid_sources[0x41]	3519	1			T3	1		T6	1		T9	1
valid_sources[0x42]	3554	1			T7	5		T12	218		T29	1
valid_sources[0x43]	3603	1			T3	1		T4	2		T6	1
valid_sources[0x44]	3544	1			T1	4		T6	2		T7	2
valid_sources[0x45]	3583	1			T3	1		T4	1		T6	1
valid_sources[0x46]	3515	1			T1	9		T35	1		T12	207
valid_sources[0x47]	3541	1			T4	1		T6	4		T35	2
valid_sources[0x48]	3645	1			T6	1		T7	1		T35	1
valid_sources[0x49]	3531	1			T4	1		T11	3		T35	2
valid_sources[0x4a]	3633	1			T7	1		T35	1		T12	234
valid_sources[0x4b]	3651	1			T7	1		T12	151		T29	1
valid_sources[0x4c]	3749	1			T6	2		T9	2		T11	1
valid_sources[0x4d]	3517	1			T3	1		T4	1		T6	1
valid_sources[0x4e]	3631	1			T4	1		T35	1		T12	208
valid_sources[0x4f]	3589	1			T3	1		T9	4		T35	4
valid_sources[0x50]	3289	1			T4	1		T6	1		T11	2
valid_sources[0x51]	3467	1			T6	1		T7	11		T9	4
valid_sources[0x52]	3497	1			T11	1		T35	3		T12	230
valid_sources[0x53]	3449	1			T6	1		T12	185		T33	4
valid_sources[0x54]	3485	1			T4	1		T6	1		T7	3
valid_sources[0x55]	3624	1			T4	1		T6	1		T9	3
valid_sources[0x56]	3609	1			T11	2		T35	2		T12	192
valid_sources[0x57]	4227	1			T4	1		T11	1		T35	2
valid_sources[0x58]	3716	1			T6	2		T9	2		T35	4
valid_sources[0x59]	3765	1			T6	2		T11	1		T12	232
valid_sources[0x5a]	3447	1			T6	1		T11	1		T12	181
valid_sources[0x5b]	3575	1			T5	1		T6	1		T9	3
valid_sources[0x5c]	3407	1			T4	3		T11	3		T35	1
valid_sources[0x5d]	3695	1			T4	1		T9	9		T11	1
valid_sources[0x5e]	3682	1			T3	1		T6	1		T7	3
valid_sources[0x5f]	3561	1			T6	1		T7	4		T9	1
valid_sources[0x60]	3574	1			T35	2		T12	211		T31	2
valid_sources[0x61]	3556	1			T1	1		T9	9		T35	1
valid_sources[0x62]	3724	1			T9	1		T35	3		T12	211
valid_sources[0x63]	3527	1			T6	3		T9	1		T35	2
valid_sources[0x64]	3502	1			T9	2		T12	177		T29	1
valid_sources[0x65]	3465	1			T6	1		T9	1		T12	194
valid_sources[0x66]	3335	1			T3	1		T6	2		T11	2
valid_sources[0x67]	3622	1			T9	6		T11	2		T35	1
valid_sources[0x68]	3433	1			T6	1		T11	1		T12	206
valid_sources[0x69]	3651	1			T9	1		T35	1		T12	213
valid_sources[0x6a]	3587	1			T3	2		T4	1		T6	1
valid_sources[0x6b]	3604	1			T5	1		T6	1		T35	2
valid_sources[0x6c]	3568	1			T6	1		T11	2		T12	189
valid_sources[0x6d]	3414	1			T4	1		T6	1		T9	6
valid_sources[0x6e]	3477	1			T4	1		T6	1		T11	1
valid_sources[0x6f]	3831	1			T6	3		T7	6		T35	2
valid_sources[0x70]	3586	1			T6	2		T35	1		T12	200
valid_sources[0x71]	3539	1			T4	1		T7	4		T35	2
valid_sources[0x72]	3713	1			T11	1		T35	3		T12	203
valid_sources[0x73]	3564	1			T6	2		T35	3		T15	3
valid_sources[0x74]	3617	1			T1	1		T6	1		T9	2
valid_sources[0x75]	3561	1			T6	3		T9	1		T35	1
valid_sources[0x76]	3558	1			T6	1		T11	1		T12	252
valid_sources[0x77]	3594	1			T3	1		T5	4		T6	1
valid_sources[0x78]	3523	1			T35	1		T12	187		T29	1
valid_sources[0x79]	3386	1			T7	1		T35	3		T12	212
valid_sources[0x7a]	3562	1			T3	1		T11	2		T35	1
valid_sources[0x7b]	3668	1			T35	1		T12	202		T33	1
valid_sources[0x7c]	3541	1			T6	1		T9	1		T35	1
valid_sources[0x7d]	3668	1			T3	2		T9	2		T11	1
valid_sources[0x7e]	3526	1			T4	2		T6	1		T35	1
valid_sources[0x7f]	3555	1			T6	3		T7	2		T9	1
valid_sources[0x80]	3607	1			T6	2		T9	2		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

218342

1

T1

11

T2

5

T3

5

values[0x0]

all_enables

biggest_size

323123

1

T12

18888

T13

7669

T14

10868

values[0x1]

all_enables

biggest_size

323856

1

T12

18961

T13

7565

T14

11016

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70555	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

678809

1

T1

33

T2

9

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	191145	1			T1	64		T2	32		T3	32
values[0x0]	258259	1			T21	5		T12	14340		T22	3
values[0x1]	299960	1			T21	3		T12	16745		T22	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33415	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

715949

1

T1

37

T2

12

T3

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2945	1			T7	1		T12	104		T36	1
valid_sources[0x01]	2403	1			T12	94		T13	62		T14	52
valid_sources[0x02]	2703	1			T7	1		T12	122		T31	1
valid_sources[0x03]	2644	1			T3	1		T35	2		T12	147
valid_sources[0x04]	2937	1			T12	25		T31	1		T32	1
valid_sources[0x05]	2838	1			T12	8		T31	3		T32	1
valid_sources[0x06]	2790	1			T7	1		T12	123		T13	47
valid_sources[0x07]	3632	1			T3	2		T12	479		T31	3
valid_sources[0x08]	2796	1			T12	165		T32	1		T13	114
valid_sources[0x09]	3275	1			T12	2		T31	2		T13	74
valid_sources[0x0a]	2865	1			T12	250		T13	62		T120	1
valid_sources[0x0b]	3052	1			T35	2		T12	9		T13	99
valid_sources[0x0c]	2616	1			T5	32		T12	149		T121	2
valid_sources[0x0d]	2829	1			T12	47		T32	1		T13	77
valid_sources[0x0e]	3127	1			T12	12		T13	47		T14	70
valid_sources[0x0f]	3502	1			T12	171		T32	1		T43	1
valid_sources[0x10]	2325	1			T12	8		T13	65		T14	78
valid_sources[0x11]	2916	1			T12	91		T32	1		T13	92
valid_sources[0x12]	2838	1			T35	2		T12	217		T13	49
valid_sources[0x13]	2582	1			T12	25		T23	3		T31	1
valid_sources[0x14]	3113	1			T3	1		T12	25		T13	111
valid_sources[0x15]	2578	1			T1	1		T12	227		T31	1
valid_sources[0x16]	2467	1			T12	13		T13	44		T122	1
valid_sources[0x17]	2425	1			T12	130		T31	1		T13	27
valid_sources[0x18]	3346	1			T12	512		T31	1		T13	122
valid_sources[0x19]	2996	1			T7	1		T12	188		T32	1
valid_sources[0x1a]	2825	1			T7	1		T12	287		T31	2
valid_sources[0x1b]	3947	1			T1	1		T12	199		T31	1
valid_sources[0x1c]	3981	1			T1	1		T7	1		T12	324
valid_sources[0x1d]	3551	1			T35	4		T12	501		T13	74
valid_sources[0x1e]	3145	1			T8	3		T12	335		T31	2
valid_sources[0x1f]	2466	1			T7	1		T12	11		T13	61
valid_sources[0x20]	2696	1			T7	1		T12	291		T13	65
valid_sources[0x21]	2721	1			T1	1		T12	232		T32	1
valid_sources[0x22]	2562	1			T7	1		T35	1		T12	73
valid_sources[0x23]	3496	1			T12	410		T31	1		T32	1
valid_sources[0x24]	3349	1			T12	460		T32	1		T71	3
valid_sources[0x25]	2758	1			T1	1		T12	59		T13	116
valid_sources[0x26]	3012	1			T7	1		T35	1		T12	353
valid_sources[0x27]	2613	1			T1	1		T7	1		T12	99
valid_sources[0x28]	2425	1			T7	1		T12	13		T13	99
valid_sources[0x29]	2935	1			T12	309		T32	1		T71	2
valid_sources[0x2a]	2884	1			T12	248		T32	2		T71	4
valid_sources[0x2b]	3084	1			T1	2		T12	192		T13	51
valid_sources[0x2c]	2975	1			T2	32		T12	62		T31	1
valid_sources[0x2d]	2398	1			T3	1		T35	3		T12	76
valid_sources[0x2e]	3209	1			T8	1		T12	326		T121	1
valid_sources[0x2f]	2752	1			T12	219		T32	1		T13	192
valid_sources[0x30]	3589	1			T7	1		T12	289		T31	1
valid_sources[0x31]	2692	1			T1	1		T21	5		T12	95
valid_sources[0x32]	2826	1			T1	2		T12	14		T32	1
valid_sources[0x33]	3256	1			T7	2		T12	292		T32	2
valid_sources[0x34]	3090	1			T1	3		T7	2		T35	2
valid_sources[0x35]	3444	1			T12	309		T32	1		T71	1
valid_sources[0x36]	2484	1			T1	2		T3	3		T12	16
valid_sources[0x37]	2750	1			T1	1		T12	11		T13	71
valid_sources[0x38]	3040	1			T35	1		T12	5		T31	2
valid_sources[0x39]	2861	1			T3	1		T12	124		T71	4
valid_sources[0x3a]	2817	1			T12	203		T28	1		T71	5
valid_sources[0x3b]	3387	1			T1	1		T3	2		T7	1
valid_sources[0x3c]	2919	1			T12	8		T13	67		T123	1
valid_sources[0x3d]	2553	1			T12	9		T71	1		T13	63
valid_sources[0x3e]	2978	1			T35	4		T21	3		T12	16
valid_sources[0x3f]	3052	1			T35	2		T12	130		T31	2
valid_sources[0x40]	2895	1			T1	1		T35	12		T12	82
valid_sources[0x41]	3286	1			T12	291		T32	2		T121	2
valid_sources[0x42]	2802	1			T1	1		T4	32		T7	1
valid_sources[0x43]	2664	1			T35	1		T12	21		T13	56
valid_sources[0x44]	2731	1			T12	10		T31	1		T32	2
valid_sources[0x45]	3519	1			T35	1		T12	243		T32	1
valid_sources[0x46]	2905	1			T12	164		T13	132		T124	1
valid_sources[0x47]	3311	1			T1	1		T12	241		T121	1
valid_sources[0x48]	3396	1			T12	198		T13	45		T14	99
valid_sources[0x49]	3467	1			T8	2		T35	6		T12	268
valid_sources[0x4a]	2535	1			T1	1		T12	76		T32	1
valid_sources[0x4b]	2603	1			T12	98		T32	1		T13	44
valid_sources[0x4c]	2950	1			T7	1		T12	277		T13	50
valid_sources[0x4d]	2600	1			T12	2		T31	1		T13	45
valid_sources[0x4e]	3022	1			T12	35		T32	1		T13	67
valid_sources[0x4f]	2405	1			T12	14		T32	2		T71	4
valid_sources[0x50]	2985	1			T1	1		T12	177		T13	80
valid_sources[0x51]	2654	1			T12	4		T13	41		T14	77
valid_sources[0x52]	2653	1			T7	1		T8	2		T12	3
valid_sources[0x53]	2970	1			T12	62		T31	1		T32	2
valid_sources[0x54]	3049	1			T12	206		T31	1		T32	1
valid_sources[0x55]	2988	1			T12	237		T13	83		T14	77
valid_sources[0x56]	2602	1			T12	5		T71	2		T13	94
valid_sources[0x57]	3025	1			T12	98		T13	46		T125	2
valid_sources[0x58]	2566	1			T7	1		T12	204		T13	66
valid_sources[0x59]	2791	1			T1	1		T12	146		T13	68
valid_sources[0x5a]	2802	1			T35	5		T12	111		T31	1
valid_sources[0x5b]	2499	1			T12	113		T13	63		T57	1
valid_sources[0x5c]	2951	1			T7	1		T12	251		T13	99
valid_sources[0x5d]	2892	1			T3	1		T12	70		T13	68
valid_sources[0x5e]	3045	1			T1	1		T7	1		T12	364
valid_sources[0x5f]	3104	1			T3	1		T12	536		T32	1
valid_sources[0x60]	2890	1			T1	2		T7	1		T12	107
valid_sources[0x61]	2727	1			T35	1		T12	8		T13	105
valid_sources[0x62]	3144	1			T12	464		T13	96		T59	1
valid_sources[0x63]	3238	1			T1	1		T12	501		T31	1
valid_sources[0x64]	2982	1			T7	1		T35	1		T12	13
valid_sources[0x65]	2887	1			T1	1		T35	1		T12	217
valid_sources[0x66]	3026	1			T12	278		T32	1		T13	49
valid_sources[0x67]	2766	1			T7	1		T24	1		T12	15
valid_sources[0x68]	2648	1			T12	54		T13	94		T124	2
valid_sources[0x69]	2790	1			T12	155		T32	1		T13	45
valid_sources[0x6a]	2907	1			T7	1		T12	5		T13	70
valid_sources[0x6b]	2732	1			T35	7		T12	184		T13	44
valid_sources[0x6c]	3885	1			T35	1		T12	235		T13	61
valid_sources[0x6d]	3555	1			T8	3		T12	217		T13	36
valid_sources[0x6e]	3331	1			T7	1		T12	227		T30	1
valid_sources[0x6f]	2424	1			T1	1		T12	14		T32	1
valid_sources[0x70]	2751	1			T3	2		T12	123		T71	1
valid_sources[0x71]	3110	1			T35	1		T12	189		T32	1
valid_sources[0x72]	3305	1			T1	1		T7	1		T35	2
valid_sources[0x73]	2921	1			T3	1		T35	3		T12	129
valid_sources[0x74]	2957	1			T35	1		T12	278		T31	1
valid_sources[0x75]	2635	1			T12	20		T13	104		T14	66
valid_sources[0x76]	3080	1			T7	1		T10	15		T12	177
valid_sources[0x77]	3104	1			T12	614		T56	2		T13	95
valid_sources[0x78]	3479	1			T1	1		T3	1		T12	394
valid_sources[0x79]	2822	1			T7	1		T12	11		T31	1
valid_sources[0x7a]	2801	1			T3	2		T7	1		T12	97
valid_sources[0x7b]	3223	1			T1	2		T7	1		T12	373
valid_sources[0x7c]	2935	1			T12	289		T32	1		T13	92
valid_sources[0x7d]	2769	1			T8	3		T35	7		T12	58
valid_sources[0x7e]	2697	1			T7	1		T35	3		T12	220
valid_sources[0x7f]	2846	1			T12	8		T31	1		T32	1
valid_sources[0x80]	3124	1			T8	3		T12	300		T13	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

172386

1

T1

33

T2

9

T3

15

values[0x0]

all_enables

biggest_size

252803

1

T21

1

T12

14061

T22

1

values[0x1]

all_enables

biggest_size

253620

1

T12

14035

T23

1

T56

1