Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1585186

1

T1

132

T2

37

T3

52

full_word

1009277

1

T1

11

T2

5

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2594123	1			T1	143		T2	42		T3	57
auto[TlIntgErrCmd]	117	1			T51	9		T52	6		T53	9
auto[TlIntgErrData]	115	1			T51	4		T52	7		T53	9
auto[TlIntgErrBoth]	108	1			T51	7		T52	7		T53	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

424725

1

T1

143

T2

42

T3

57

auto[1]

2169738

1

T12

125124

T13

49067

T14

71052

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	185451	1			T1	132		T2	37		T3	52
auto[TlIntgErrNone]	partial	auto[1]	1399426	1			T12	80203		T13	31174		T14	45166
auto[TlIntgErrNone]	full_word	auto[0]	239133	1			T1	11		T2	5		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	770113	1			T12	44921		T13	17893		T14	25886
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T51	2		T53	5		T109	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T51	4		T52	6		T53	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T51	1		T115	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T51	2		T53	2		T116	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T51	2		T52	4		T53	1
auto[TlIntgErrData]	partial	auto[1]	61	1			T51	1		T52	2		T53	6
auto[TlIntgErrData]	full_word	auto[0]	6	1			T52	1		T53	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T51	1		T53	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T51	2		T52	1		T53	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T51	4		T52	5		T109	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T109	1		T117	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T51	1		T52	1		T112	1