Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1461333

1

T1

9

T2

15

T6

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	405021	1			T1	9		T2	194		T6	80
values[0x0]	552127	1			T16	36860		T11	21727		T26	7498
values[0x1]	571016	1			T16	38181		T11	22473		T26	7799

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34093	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1494071

1

T1

9

T2

119

T6

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5983	1			T2	1		T7	2		T16	397
valid_sources[0x01]	7391	1			T7	2		T16	377		T11	216
valid_sources[0x02]	5330	1			T6	1		T7	2		T16	388
valid_sources[0x03]	5678	1			T7	1		T16	413		T11	328
valid_sources[0x04]	6332	1			T6	1		T16	383		T17	1
valid_sources[0x05]	6001	1			T7	6		T16	415		T11	215
valid_sources[0x06]	6425	1			T6	1		T16	357		T17	1
valid_sources[0x07]	6073	1			T2	6		T16	416		T11	205
valid_sources[0x08]	6146	1			T16	411		T11	231		T13	4
valid_sources[0x09]	5345	1			T16	327		T11	189		T26	80
valid_sources[0x0a]	5270	1			T7	5		T14	1		T16	440
valid_sources[0x0b]	6381	1			T14	1		T16	366		T11	288
valid_sources[0x0c]	6104	1			T6	2		T16	444		T11	259
valid_sources[0x0d]	5910	1			T2	14		T6	1		T15	25
valid_sources[0x0e]	6728	1			T6	2		T7	1		T14	1
valid_sources[0x0f]	5895	1			T16	370		T11	319		T70	1
valid_sources[0x10]	5854	1			T16	372		T11	246		T71	1
valid_sources[0x11]	5395	1			T14	2		T16	381		T11	239
valid_sources[0x12]	5375	1			T7	1		T16	408		T11	299
valid_sources[0x13]	5406	1			T7	2		T16	439		T11	215
valid_sources[0x14]	5843	1			T16	457		T11	211		T105	12
valid_sources[0x15]	5649	1			T16	365		T11	172		T70	1
valid_sources[0x16]	6451	1			T6	1		T7	2		T16	369
valid_sources[0x17]	5329	1			T6	2		T7	1		T16	359
valid_sources[0x18]	5546	1			T14	1		T16	351		T11	210
valid_sources[0x19]	5970	1			T6	1		T7	2		T16	414
valid_sources[0x1a]	6289	1			T14	1		T16	391		T11	265
valid_sources[0x1b]	7020	1			T6	1		T16	394		T11	263
valid_sources[0x1c]	5746	1			T16	438		T17	2		T11	177
valid_sources[0x1d]	5371	1			T6	1		T7	1		T14	1
valid_sources[0x1e]	6200	1			T16	416		T11	225		T118	1
valid_sources[0x1f]	6487	1			T6	1		T16	378		T11	259
valid_sources[0x20]	5498	1			T1	1		T6	1		T16	362
valid_sources[0x21]	6848	1			T14	2		T16	422		T17	2
valid_sources[0x22]	5621	1			T2	3		T16	443		T11	222
valid_sources[0x23]	6025	1			T16	420		T11	264		T26	75
valid_sources[0x24]	5769	1			T16	443		T11	186		T69	1
valid_sources[0x25]	6234	1			T16	403		T17	1		T11	275
valid_sources[0x26]	5787	1			T14	1		T16	402		T11	298
valid_sources[0x27]	5602	1			T7	2		T14	1		T16	428
valid_sources[0x28]	5744	1			T6	1		T7	5		T16	385
valid_sources[0x29]	5721	1			T14	2		T16	438		T17	1
valid_sources[0x2a]	5549	1			T2	6		T16	418		T17	1
valid_sources[0x2b]	5608	1			T6	2		T16	410		T11	238
valid_sources[0x2c]	5451	1			T14	2		T16	359		T11	246
valid_sources[0x2d]	5637	1			T6	1		T7	1		T16	383
valid_sources[0x2e]	5357	1			T16	360		T11	224		T70	2
valid_sources[0x2f]	7351	1			T16	372		T11	252		T69	4
valid_sources[0x30]	7126	1			T16	392		T11	249		T105	7
valid_sources[0x31]	6024	1			T6	1		T7	7		T16	355
valid_sources[0x32]	5454	1			T6	1		T16	401		T17	1
valid_sources[0x33]	5727	1			T7	2		T16	388		T11	256
valid_sources[0x34]	5845	1			T16	430		T11	221		T69	1
valid_sources[0x35]	6156	1			T7	1		T16	416		T17	1
valid_sources[0x36]	5654	1			T16	494		T11	262		T118	1
valid_sources[0x37]	5273	1			T6	1		T15	32		T16	409
valid_sources[0x38]	6438	1			T6	2		T14	1		T16	444
valid_sources[0x39]	5977	1			T7	1		T16	426		T11	226
valid_sources[0x3a]	6236	1			T16	364		T17	2		T11	262
valid_sources[0x3b]	5888	1			T7	2		T16	400		T17	1
valid_sources[0x3c]	5943	1			T7	4		T16	404		T11	219
valid_sources[0x3d]	6449	1			T1	1		T7	1		T14	1
valid_sources[0x3e]	5757	1			T16	384		T17	1		T11	192
valid_sources[0x3f]	6966	1			T2	10		T14	1		T15	10
valid_sources[0x40]	6739	1			T16	403		T11	229		T70	1
valid_sources[0x41]	5959	1			T14	1		T16	373		T17	1
valid_sources[0x42]	5481	1			T7	2		T16	362		T11	201
valid_sources[0x43]	6454	1			T6	1		T16	480		T17	1
valid_sources[0x44]	7033	1			T7	4		T14	1		T16	370
valid_sources[0x45]	6381	1			T6	1		T7	1		T16	388
valid_sources[0x46]	6444	1			T2	12		T16	329		T11	204
valid_sources[0x47]	6046	1			T7	2		T14	1		T16	343
valid_sources[0x48]	5679	1			T2	1		T7	2		T14	1
valid_sources[0x49]	6361	1			T14	1		T16	442		T11	220
valid_sources[0x4a]	5963	1			T16	400		T11	238		T105	3
valid_sources[0x4b]	6000	1			T16	387		T17	1		T11	195
valid_sources[0x4c]	5241	1			T7	3		T16	373		T17	1
valid_sources[0x4d]	6439	1			T16	403		T11	203		T69	1
valid_sources[0x4e]	6663	1			T7	2		T16	422		T11	225
valid_sources[0x4f]	6699	1			T6	2		T16	378		T11	198
valid_sources[0x50]	5979	1			T16	460		T11	217		T118	1
valid_sources[0x51]	5955	1			T6	2		T7	1		T16	401
valid_sources[0x52]	5460	1			T6	1		T16	456		T11	263
valid_sources[0x53]	6422	1			T16	348		T17	1		T11	257
valid_sources[0x54]	5304	1			T16	362		T17	1		T11	199
valid_sources[0x55]	6256	1			T16	383		T11	243		T118	1
valid_sources[0x56]	5764	1			T6	1		T7	2		T16	355
valid_sources[0x57]	6163	1			T14	1		T16	366		T11	201
valid_sources[0x58]	5531	1			T7	1		T16	343		T17	1
valid_sources[0x59]	5912	1			T7	1		T16	381		T11	235
valid_sources[0x5a]	5226	1			T2	22		T6	1		T7	6
valid_sources[0x5b]	5348	1			T7	4		T16	397		T11	202
valid_sources[0x5c]	6272	1			T16	436		T17	1		T11	341
valid_sources[0x5d]	5958	1			T1	2		T16	449		T11	200
valid_sources[0x5e]	7108	1			T2	12		T14	1		T16	407
valid_sources[0x5f]	6877	1			T6	1		T16	381		T11	242
valid_sources[0x60]	5587	1			T2	10		T6	1		T16	389
valid_sources[0x61]	5365	1			T6	2		T14	1		T16	362
valid_sources[0x62]	5274	1			T16	379		T17	1		T11	183
valid_sources[0x63]	5381	1			T6	2		T14	1		T16	418
valid_sources[0x64]	5718	1			T14	1		T16	376		T11	165
valid_sources[0x65]	5429	1			T14	1		T16	416		T17	2
valid_sources[0x66]	5611	1			T2	11		T7	1		T16	328
valid_sources[0x67]	5919	1			T6	1		T16	446		T11	259
valid_sources[0x68]	6095	1			T6	1		T7	1		T16	352
valid_sources[0x69]	6126	1			T6	1		T16	378		T11	215
valid_sources[0x6a]	5584	1			T16	405		T11	155		T118	3
valid_sources[0x6b]	5333	1			T7	3		T16	359		T11	247
valid_sources[0x6c]	6178	1			T7	2		T16	384		T11	247
valid_sources[0x6d]	5269	1			T6	2		T8	1		T16	369
valid_sources[0x6e]	5306	1			T14	2		T16	396		T11	185
valid_sources[0x6f]	5972	1			T7	5		T16	397		T11	247
valid_sources[0x70]	5658	1			T16	436		T11	178		T12	1
valid_sources[0x71]	6809	1			T7	3		T16	357		T17	1
valid_sources[0x72]	5689	1			T7	1		T14	1		T16	414
valid_sources[0x73]	6566	1			T7	8		T16	384		T11	294
valid_sources[0x74]	5460	1			T7	1		T16	388		T17	1
valid_sources[0x75]	5856	1			T2	4		T7	2		T16	422
valid_sources[0x76]	6059	1			T16	335		T17	1		T11	236
valid_sources[0x77]	5773	1			T16	418		T11	270		T71	1
valid_sources[0x78]	5716	1			T6	1		T7	1		T16	400
valid_sources[0x79]	5719	1			T16	352		T17	1		T11	281
valid_sources[0x7a]	6324	1			T1	1		T2	11		T16	366
valid_sources[0x7b]	6377	1			T7	2		T8	1		T14	1
valid_sources[0x7c]	6494	1			T7	2		T16	437		T11	224
valid_sources[0x7d]	6433	1			T7	1		T16	402		T11	289
valid_sources[0x7e]	5801	1			T14	2		T16	439		T17	1
valid_sources[0x7f]	6984	1			T6	1		T16	380		T11	284
valid_sources[0x80]	5538	1			T16	364		T17	1		T11	273

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

368375

1

T1

9

T2

15

T6

6

values[0x0]

all_enables

biggest_size

547258

1

T16

36506

T11

21533

T26

7434

values[0x1]

all_enables

biggest_size

545700

1

T16

36541

T11

21475

T26

7408

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	111985	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1124772

1

T1

16

T5

1

T6

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	311474	1			T1	23		T3	1		T4	1
values[0x0]	428150	1			T10	7		T24	1		T16	27199
values[0x1]	497133	1			T10	10		T16	32006		T11	18137

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50513	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1186244

1

T1

17

T4

1

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4696	1			T16	348		T11	192		T26	63
valid_sources[0x01]	4492	1			T16	330		T11	153		T13	1
valid_sources[0x02]	4882	1			T16	283		T11	152		T38	2
valid_sources[0x03]	5197	1			T16	289		T11	179		T26	69
valid_sources[0x04]	4803	1			T16	295		T11	167		T13	3
valid_sources[0x05]	4755	1			T15	1		T16	334		T11	126
valid_sources[0x06]	4636	1			T16	291		T11	241		T26	42
valid_sources[0x07]	4870	1			T6	3		T16	289		T11	174
valid_sources[0x08]	5968	1			T16	320		T11	213		T26	67
valid_sources[0x09]	4824	1			T16	287		T11	186		T38	1
valid_sources[0x0a]	4895	1			T16	307		T11	142		T41	2
valid_sources[0x0b]	4938	1			T16	314		T11	166		T26	69
valid_sources[0x0c]	4641	1			T16	268		T11	192		T106	1
valid_sources[0x0d]	5608	1			T16	315		T11	178		T26	71
valid_sources[0x0e]	5475	1			T6	6		T16	275		T11	207
valid_sources[0x0f]	4412	1			T15	2		T16	302		T11	177
valid_sources[0x10]	4871	1			T16	325		T11	204		T41	1
valid_sources[0x11]	5430	1			T16	336		T11	170		T41	2
valid_sources[0x12]	4544	1			T15	1		T16	286		T11	192
valid_sources[0x13]	4726	1			T16	323		T11	208		T26	64
valid_sources[0x14]	5196	1			T16	255		T11	200		T40	2
valid_sources[0x15]	4469	1			T16	235		T11	157		T18	1
valid_sources[0x16]	4615	1			T16	303		T11	174		T26	74
valid_sources[0x17]	4620	1			T16	348		T11	139		T106	1
valid_sources[0x18]	4515	1			T16	305		T11	159		T38	1
valid_sources[0x19]	5467	1			T16	328		T11	211		T26	56
valid_sources[0x1a]	4592	1			T10	1		T15	1		T16	294
valid_sources[0x1b]	4746	1			T15	1		T16	293		T11	186
valid_sources[0x1c]	4957	1			T16	267		T11	179		T13	1
valid_sources[0x1d]	4421	1			T6	2		T16	270		T11	181
valid_sources[0x1e]	4105	1			T16	351		T11	181		T22	1
valid_sources[0x1f]	4366	1			T16	308		T11	171		T26	74
valid_sources[0x20]	5221	1			T16	258		T11	163		T13	2
valid_sources[0x21]	4922	1			T16	229		T11	209		T40	1
valid_sources[0x22]	5038	1			T16	324		T11	174		T70	1
valid_sources[0x23]	4811	1			T16	329		T11	194		T18	1
valid_sources[0x24]	4859	1			T15	1		T16	353		T11	177
valid_sources[0x25]	4655	1			T16	274		T11	178		T26	58
valid_sources[0x26]	4696	1			T16	305		T11	187		T13	1
valid_sources[0x27]	4633	1			T16	257		T11	170		T26	63
valid_sources[0x28]	5210	1			T16	293		T11	168		T18	1
valid_sources[0x29]	4768	1			T16	271		T11	192		T26	67
valid_sources[0x2a]	4806	1			T16	335		T11	228		T70	2
valid_sources[0x2b]	4332	1			T16	305		T11	174		T39	10
valid_sources[0x2c]	4662	1			T16	338		T11	123		T70	4
valid_sources[0x2d]	4878	1			T16	282		T11	161		T18	1
valid_sources[0x2e]	4815	1			T15	2		T16	318		T11	165
valid_sources[0x2f]	4417	1			T16	312		T11	198		T41	1
valid_sources[0x30]	4886	1			T16	307		T11	224		T72	1
valid_sources[0x31]	4891	1			T15	1		T16	316		T11	146
valid_sources[0x32]	4732	1			T16	298		T11	165		T72	1
valid_sources[0x33]	5233	1			T9	1		T15	1		T16	346
valid_sources[0x34]	4845	1			T15	1		T16	357		T11	196
valid_sources[0x35]	4435	1			T16	266		T11	168		T18	1
valid_sources[0x36]	5008	1			T5	1		T16	310		T11	141
valid_sources[0x37]	5197	1			T16	369		T11	185		T106	1
valid_sources[0x38]	5009	1			T16	325		T11	134		T26	68
valid_sources[0x39]	4375	1			T16	394		T11	204		T72	1
valid_sources[0x3a]	4476	1			T16	273		T11	196		T106	3
valid_sources[0x3b]	4706	1			T15	1		T16	298		T11	169
valid_sources[0x3c]	4882	1			T16	347		T11	184		T23	2
valid_sources[0x3d]	5065	1			T8	6		T15	1		T16	304
valid_sources[0x3e]	4851	1			T16	329		T11	190		T38	1
valid_sources[0x3f]	4764	1			T16	337		T11	200		T13	2
valid_sources[0x40]	5321	1			T16	331		T11	187		T26	64
valid_sources[0x41]	5022	1			T10	1		T16	300		T11	170
valid_sources[0x42]	4901	1			T6	3		T15	1		T16	302
valid_sources[0x43]	5048	1			T15	1		T16	319		T11	171
valid_sources[0x44]	4500	1			T10	1		T16	256		T11	177
valid_sources[0x45]	4890	1			T16	290		T11	163		T38	1
valid_sources[0x46]	5025	1			T16	273		T11	228		T26	64
valid_sources[0x47]	4693	1			T10	1		T16	277		T11	183
valid_sources[0x48]	4652	1			T16	353		T11	185		T26	69
valid_sources[0x49]	4278	1			T10	1		T16	302		T11	135
valid_sources[0x4a]	4705	1			T16	291		T11	157		T13	1
valid_sources[0x4b]	5030	1			T16	315		T11	201		T18	2
valid_sources[0x4c]	5260	1			T16	393		T11	196		T38	3
valid_sources[0x4d]	5305	1			T15	1		T16	306		T11	195
valid_sources[0x4e]	5116	1			T16	245		T11	217		T69	64
valid_sources[0x4f]	4425	1			T16	292		T11	173		T26	73
valid_sources[0x50]	4778	1			T16	322		T11	150		T72	1
valid_sources[0x51]	4769	1			T16	290		T11	164		T26	75
valid_sources[0x52]	4557	1			T16	320		T11	162		T70	1
valid_sources[0x53]	4381	1			T16	303		T11	184		T41	1
valid_sources[0x54]	4586	1			T8	5		T16	282		T11	200
valid_sources[0x55]	5131	1			T15	1		T16	275		T11	104
valid_sources[0x56]	4922	1			T15	3		T16	302		T11	212
valid_sources[0x57]	4562	1			T16	290		T11	202		T13	1
valid_sources[0x58]	4530	1			T6	10		T16	263		T11	144
valid_sources[0x59]	5120	1			T15	1		T16	319		T11	168
valid_sources[0x5a]	4538	1			T16	366		T11	171		T26	85
valid_sources[0x5b]	4522	1			T16	290		T11	181		T26	76
valid_sources[0x5c]	5114	1			T15	1		T16	337		T11	225
valid_sources[0x5d]	4990	1			T16	223		T11	233		T106	1
valid_sources[0x5e]	4622	1			T10	1		T16	309		T11	163
valid_sources[0x5f]	4983	1			T16	237		T11	205		T26	58
valid_sources[0x60]	4895	1			T16	356		T11	204		T22	3
valid_sources[0x61]	4501	1			T16	366		T11	159		T72	1
valid_sources[0x62]	4508	1			T16	241		T11	204		T72	1
valid_sources[0x63]	4753	1			T15	1		T16	284		T11	187
valid_sources[0x64]	4845	1			T16	265		T27	1		T11	164
valid_sources[0x65]	5083	1			T16	294		T11	164		T13	1
valid_sources[0x66]	4599	1			T16	329		T11	154		T26	69
valid_sources[0x67]	4449	1			T16	309		T11	214		T13	1
valid_sources[0x68]	5099	1			T16	265		T11	204		T26	67
valid_sources[0x69]	4915	1			T15	1		T16	362		T11	203
valid_sources[0x6a]	4291	1			T10	1		T16	289		T11	131
valid_sources[0x6b]	4464	1			T15	1		T16	400		T11	168
valid_sources[0x6c]	4269	1			T16	333		T11	153		T26	72
valid_sources[0x6d]	4868	1			T8	1		T16	318		T11	146
valid_sources[0x6e]	5218	1			T16	300		T11	192		T22	1
valid_sources[0x6f]	4620	1			T16	321		T11	195		T26	63
valid_sources[0x70]	5086	1			T16	325		T11	168		T18	1
valid_sources[0x71]	5079	1			T16	248		T11	123		T70	1
valid_sources[0x72]	5320	1			T16	253		T11	153		T26	65
valid_sources[0x73]	5044	1			T16	296		T11	165		T72	1
valid_sources[0x74]	4575	1			T16	247		T11	173		T38	1
valid_sources[0x75]	4826	1			T16	296		T11	140		T106	2
valid_sources[0x76]	4687	1			T16	299		T11	181		T26	71
valid_sources[0x77]	4886	1			T16	298		T11	159		T26	52
valid_sources[0x78]	4746	1			T16	318		T11	230		T26	68
valid_sources[0x79]	4349	1			T16	261		T11	235		T18	1
valid_sources[0x7a]	4840	1			T16	385		T11	176		T26	68
valid_sources[0x7b]	5183	1			T16	311		T11	181		T26	77
valid_sources[0x7c]	5034	1			T15	2		T16	274		T11	214
valid_sources[0x7d]	5252	1			T16	330		T11	139		T18	1
valid_sources[0x7e]	5124	1			T16	361		T11	164		T18	1
valid_sources[0x7f]	4903	1			T15	1		T16	308		T11	174
valid_sources[0x80]	4495	1			T14	32		T16	262		T11	168

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

285401

1

T1

16

T5

1

T6

24

values[0x0]

all_enables

biggest_size

419284

1

T10

4

T16

26703

T11

15881

values[0x1]

all_enables

biggest_size

420087

1

T16

26967

T11

15597

T22

2