Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2683013

1

T2

179

T6

74

T7

204

full_word

1705807

1

T1

6

T2

15

T6

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4388560	1			T1	6		T2	194		T6	80
auto[TlIntgErrCmd]	80	1			T54	8		T55	3		T56	5
auto[TlIntgErrData]	94	1			T54	7		T55	2		T56	8
auto[TlIntgErrBoth]	86	1			T54	5		T55	5		T56	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

701022

1

T1

6

T2

194

T6

80

auto[1]

3687798

1

T16

245049

T11

142753

T26

51859

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	297397	1			T2	179		T6	74		T7	204
auto[TlIntgErrNone]	partial	auto[1]	2385377	1			T16	158129		T11	91616		T26	34110
auto[TlIntgErrNone]	full_word	auto[0]	403514	1			T1	6		T2	15		T6	6
auto[TlIntgErrNone]	full_word	auto[1]	1302272	1			T16	86920		T11	51137		T26	17749
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T54	2		T55	3		T56	3
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T54	5		T56	2		T108	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T113	1		T114	1		T109	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T54	1		T110	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T54	3		T56	6		T108	4
auto[TlIntgErrData]	partial	auto[1]	38	1			T54	4		T55	2		T56	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T115	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T112	1		T113	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1			T54	2		T55	2		T56	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T54	3		T55	3		T56	6
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T112	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T110	1		T117	1		T116	1