Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3043864

1

T4

187

T5

75

T8

145

full_word

1939338

1

T1

2

T2

2

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4982892	1			T1	2		T2	2		T3	2
auto[TlIntgErrCmd]	107	1			T63	4		T64	4		T65	5
auto[TlIntgErrData]	105	1			T63	8		T64	3		T65	2
auto[TlIntgErrBoth]	98	1			T63	8		T64	3		T65	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

790258

1

T1

2

T2

2

T3

2

auto[1]

4192944

1

T21

157528

T22

182008

T23

94137

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	332292	1			T4	187		T5	75		T8	145
auto[TlIntgErrNone]	partial	auto[1]	2711290	1			T21	101423		T22	117683		T23	58599
auto[TlIntgErrNone]	full_word	auto[0]	457832	1			T1	2		T2	2		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	1481478	1			T21	56105		T22	64325		T23	35538
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T63	1		T65	1		T111	2
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T63	2		T64	4		T65	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T113	1		T116	2		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T63	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1			T63	4		T64	1		T111	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T63	4		T64	2		T65	1
auto[TlIntgErrData]	full_word	auto[0]	11	1			T65	1		T115	2		T117	3
auto[TlIntgErrData]	full_word	auto[1]	5	1			T116	3		T120	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T63	3		T65	2		T111	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T63	4		T64	3		T65	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T122	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T63	1		T118	2		T114	1