Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1581523

1

T2

6

T3

6

T5

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	433425	1			T2	6		T3	6		T5	213
values[0x0]	597529	1			T15	79374		T18	40883		T19	51678
values[0x1]	618014	1			T15	81956		T18	42228		T19	53815

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1614166

1

T2

6

T3

6

T5

132

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5661	1			T7	2		T13	1		T72	1
valid_sources[0x01]	6751	1			T5	1		T6	1		T7	3
valid_sources[0x02]	6441	1			T5	2		T7	3		T72	2
valid_sources[0x03]	5996	1			T7	1		T23	1		T15	417
valid_sources[0x04]	6426	1			T5	2		T7	5		T23	2
valid_sources[0x05]	5700	1			T5	3		T6	3		T8	1
valid_sources[0x06]	5164	1			T5	1		T7	1		T20	1
valid_sources[0x07]	5586	1			T5	3		T7	1		T8	1
valid_sources[0x08]	6545	1			T6	1		T7	2		T8	2
valid_sources[0x09]	7595	1			T8	1		T25	1		T15	1644
valid_sources[0x0a]	5789	1			T5	2		T6	1		T7	5
valid_sources[0x0b]	6313	1			T5	1		T7	2		T8	1
valid_sources[0x0c]	6829	1			T7	2		T25	9		T20	4
valid_sources[0x0d]	8011	1			T25	2		T15	478		T17	1
valid_sources[0x0e]	6997	1			T5	2		T8	1		T72	1
valid_sources[0x0f]	6157	1			T7	1		T20	1		T15	793
valid_sources[0x10]	5958	1			T7	8		T25	1		T20	4
valid_sources[0x11]	6898	1			T7	1		T8	1		T25	1
valid_sources[0x12]	5790	1			T5	2		T25	2		T72	1
valid_sources[0x13]	6749	1			T5	3		T6	1		T72	1
valid_sources[0x14]	6200	1			T5	1		T25	1		T15	1294
valid_sources[0x15]	7806	1			T5	1		T6	1		T8	2
valid_sources[0x16]	5135	1			T7	2		T23	1		T15	142
valid_sources[0x17]	6376	1			T8	2		T72	1		T18	421
valid_sources[0x18]	5705	1			T7	1		T25	1		T20	2
valid_sources[0x19]	5944	1			T7	2		T20	1		T23	3
valid_sources[0x1a]	6063	1			T5	2		T7	4		T20	1
valid_sources[0x1b]	9070	1			T5	1		T7	3		T25	2
valid_sources[0x1c]	5368	1			T6	1		T23	2		T15	296
valid_sources[0x1d]	6820	1			T8	1		T25	2		T23	1
valid_sources[0x1e]	6904	1			T5	1		T7	2		T72	1
valid_sources[0x1f]	5332	1			T6	1		T7	3		T25	3
valid_sources[0x20]	6859	1			T5	1		T7	1		T8	3
valid_sources[0x21]	6842	1			T5	1		T7	2		T72	1
valid_sources[0x22]	7636	1			T5	2		T8	1		T23	1
valid_sources[0x23]	5777	1			T7	1		T25	3		T23	1
valid_sources[0x24]	5954	1			T7	3		T15	782		T125	1
valid_sources[0x25]	7527	1			T5	1		T20	2		T23	2
valid_sources[0x26]	5352	1			T25	7		T23	3		T15	454
valid_sources[0x27]	5609	1			T5	1		T6	1		T15	214
valid_sources[0x28]	5762	1			T7	1		T25	1		T23	7
valid_sources[0x29]	6019	1			T7	1		T25	2		T23	1
valid_sources[0x2a]	5435	1			T7	5		T8	1		T25	4
valid_sources[0x2b]	5375	1			T5	5		T7	1		T8	2
valid_sources[0x2c]	9148	1			T7	7		T25	4		T20	1
valid_sources[0x2d]	5669	1			T3	1		T5	4		T7	3
valid_sources[0x2e]	5684	1			T20	1		T72	2		T15	560
valid_sources[0x2f]	5281	1			T7	2		T23	4		T72	1
valid_sources[0x30]	6329	1			T5	2		T8	4		T15	485
valid_sources[0x31]	5565	1			T5	1		T7	1		T8	1
valid_sources[0x32]	5499	1			T7	2		T25	2		T72	1
valid_sources[0x33]	6526	1			T25	2		T72	1		T15	417
valid_sources[0x34]	6799	1			T7	3		T23	1		T15	1009
valid_sources[0x35]	6182	1			T5	2		T7	3		T25	2
valid_sources[0x36]	7587	1			T7	4		T8	2		T25	1
valid_sources[0x37]	6562	1			T25	2		T23	1		T72	1
valid_sources[0x38]	5589	1			T5	1		T23	2		T15	335
valid_sources[0x39]	8222	1			T23	3		T72	3		T15	2326
valid_sources[0x3a]	5624	1			T5	2		T7	3		T25	1
valid_sources[0x3b]	7402	1			T7	6		T25	1		T15	2147
valid_sources[0x3c]	5478	1			T5	3		T7	1		T8	1
valid_sources[0x3d]	6087	1			T5	1		T25	3		T20	1
valid_sources[0x3e]	8056	1			T15	1543		T18	412		T126	1
valid_sources[0x3f]	7485	1			T5	1		T25	1		T23	5
valid_sources[0x40]	7678	1			T5	2		T7	2		T15	412
valid_sources[0x41]	5827	1			T5	1		T7	3		T8	3
valid_sources[0x42]	6408	1			T5	1		T7	1		T15	1393
valid_sources[0x43]	6838	1			T25	4		T23	3		T72	1
valid_sources[0x44]	5392	1			T7	1		T8	1		T72	4
valid_sources[0x45]	8043	1			T6	1		T20	3		T15	671
valid_sources[0x46]	6137	1			T5	1		T7	1		T8	1
valid_sources[0x47]	8561	1			T5	1		T7	2		T20	2
valid_sources[0x48]	4915	1			T8	2		T25	1		T20	1
valid_sources[0x49]	8359	1			T8	2		T20	1		T23	1
valid_sources[0x4a]	5898	1			T5	1		T7	2		T8	2
valid_sources[0x4b]	5783	1			T6	1		T7	1		T25	1
valid_sources[0x4c]	5453	1			T7	1		T15	323		T18	472
valid_sources[0x4d]	6254	1			T5	2		T25	1		T20	1
valid_sources[0x4e]	5588	1			T5	3		T7	4		T8	5
valid_sources[0x4f]	6218	1			T20	1		T23	2		T72	1
valid_sources[0x50]	5488	1			T5	2		T8	2		T25	1
valid_sources[0x51]	6955	1			T7	1		T20	1		T23	2
valid_sources[0x52]	6072	1			T5	4		T25	2		T15	680
valid_sources[0x53]	5229	1			T7	1		T25	3		T23	1
valid_sources[0x54]	6123	1			T3	1		T7	3		T25	1
valid_sources[0x55]	7126	1			T5	2		T6	1		T8	3
valid_sources[0x56]	6532	1			T5	1		T7	1		T8	1
valid_sources[0x57]	5909	1			T5	1		T7	4		T15	570
valid_sources[0x58]	6479	1			T5	2		T7	1		T25	6
valid_sources[0x59]	7770	1			T5	2		T6	2		T25	1
valid_sources[0x5a]	6291	1			T8	4		T23	6		T72	4
valid_sources[0x5b]	6066	1			T3	1		T7	8		T23	1
valid_sources[0x5c]	7758	1			T7	1		T8	2		T25	1
valid_sources[0x5d]	7716	1			T6	1		T7	1		T72	2
valid_sources[0x5e]	5737	1			T7	4		T25	3		T23	12
valid_sources[0x5f]	6597	1			T5	1		T7	1		T25	4
valid_sources[0x60]	5320	1			T5	1		T7	2		T20	2
valid_sources[0x61]	6176	1			T5	2		T6	1		T7	2
valid_sources[0x62]	6961	1			T7	3		T8	2		T25	2
valid_sources[0x63]	7372	1			T5	2		T7	3		T8	3
valid_sources[0x64]	5712	1			T7	4		T72	2		T15	546
valid_sources[0x65]	7117	1			T5	2		T7	3		T20	3
valid_sources[0x66]	6282	1			T7	2		T8	4		T23	1
valid_sources[0x67]	7247	1			T5	1		T7	5		T8	1
valid_sources[0x68]	5530	1			T7	2		T25	8		T72	3
valid_sources[0x69]	6059	1			T7	1		T8	1		T25	2
valid_sources[0x6a]	6576	1			T8	1		T25	1		T20	2
valid_sources[0x6b]	6452	1			T5	2		T7	3		T8	2
valid_sources[0x6c]	6975	1			T5	1		T8	2		T15	633
valid_sources[0x6d]	6726	1			T6	1		T7	1		T15	1356
valid_sources[0x6e]	6235	1			T5	2		T8	1		T20	1
valid_sources[0x6f]	7752	1			T5	1		T25	3		T23	2
valid_sources[0x70]	7937	1			T5	4		T7	3		T23	2
valid_sources[0x71]	6090	1			T72	1		T15	831		T18	409
valid_sources[0x72]	7285	1			T3	1		T5	1		T7	1
valid_sources[0x73]	5944	1			T5	2		T7	3		T20	1
valid_sources[0x74]	5847	1			T6	1		T7	1		T23	3
valid_sources[0x75]	7072	1			T5	1		T7	1		T8	1
valid_sources[0x76]	6518	1			T5	2		T7	3		T8	1
valid_sources[0x77]	6188	1			T7	4		T8	1		T20	1
valid_sources[0x78]	6418	1			T5	1		T7	1		T8	2
valid_sources[0x79]	6136	1			T5	1		T6	1		T8	1
valid_sources[0x7a]	7588	1			T8	2		T25	5		T15	826
valid_sources[0x7b]	7103	1			T6	2		T15	1448		T18	411
valid_sources[0x7c]	5046	1			T6	1		T7	1		T8	2
valid_sources[0x7d]	7331	1			T5	3		T7	1		T25	2
valid_sources[0x7e]	7262	1			T7	1		T20	1		T23	2
valid_sources[0x7f]	7192	1			T5	2		T8	1		T23	3
valid_sources[0x80]	5840	1			T5	1		T7	3		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

397885

1

T2

6

T3

6

T5

21

values[0x0]

all_enables

biggest_size

592381

1

T15

78672

T18

40525

T19

51252

values[0x1]

all_enables

biggest_size

591257

1

T15

78308

T18

40432

T19

51555

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121518	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1201323

1

T2

16

T3

16

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	332359	1			T2	26		T3	29		T6	32
values[0x0]	459064	1			T4	7		T10	1		T12	3
values[0x1]	531418	1			T1	2		T4	6		T10	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54714	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1268127

1

T2

17

T3

19

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4830	1			T15	629		T18	348		T19	463
valid_sources[0x01]	5457	1			T4	1		T15	640		T18	350
valid_sources[0x02]	5079	1			T23	1		T15	704		T18	182
valid_sources[0x03]	5610	1			T20	3		T23	2		T15	669
valid_sources[0x04]	5076	1			T13	1		T15	729		T18	335
valid_sources[0x05]	4726	1			T70	1		T23	4		T15	685
valid_sources[0x06]	4395	1			T20	1		T21	1		T15	622
valid_sources[0x07]	4903	1			T21	1		T23	1		T15	598
valid_sources[0x08]	4783	1			T3	3		T12	1		T15	670
valid_sources[0x09]	4123	1			T1	1		T2	1		T15	605
valid_sources[0x0a]	4651	1			T20	1		T70	1		T15	607
valid_sources[0x0b]	4505	1			T21	2		T15	707		T18	442
valid_sources[0x0c]	5360	1			T15	748		T18	364		T19	459
valid_sources[0x0d]	5316	1			T12	1		T15	627		T26	3
valid_sources[0x0e]	5360	1			T15	537		T18	311		T19	473
valid_sources[0x0f]	5401	1			T23	2		T15	676		T18	316
valid_sources[0x10]	5133	1			T23	1		T15	604		T18	303
valid_sources[0x11]	5181	1			T20	2		T21	1		T23	4
valid_sources[0x12]	4925	1			T13	1		T15	622		T18	309
valid_sources[0x13]	5115	1			T20	2		T15	736		T18	231
valid_sources[0x14]	5649	1			T15	684		T59	7		T18	340
valid_sources[0x15]	5669	1			T23	1		T15	703		T18	278
valid_sources[0x16]	5965	1			T20	1		T15	684		T18	317
valid_sources[0x17]	5409	1			T4	1		T21	1		T15	762
valid_sources[0x18]	5630	1			T15	687		T46	1		T18	311
valid_sources[0x19]	4945	1			T6	32		T15	603		T18	342
valid_sources[0x1a]	4890	1			T23	4		T15	648		T18	307
valid_sources[0x1b]	5489	1			T31	13		T15	640		T18	385
valid_sources[0x1c]	4721	1			T4	1		T15	733		T18	310
valid_sources[0x1d]	5045	1			T30	2		T20	2		T15	659
valid_sources[0x1e]	6033	1			T2	2		T15	639		T18	341
valid_sources[0x1f]	4691	1			T15	724		T59	3		T18	345
valid_sources[0x20]	5405	1			T15	674		T18	276		T19	497
valid_sources[0x21]	5534	1			T30	6		T20	1		T15	647
valid_sources[0x22]	4938	1			T15	697		T18	365		T19	437
valid_sources[0x23]	5156	1			T20	1		T15	663		T18	236
valid_sources[0x24]	5657	1			T20	1		T21	1		T15	796
valid_sources[0x25]	5124	1			T15	734		T61	1		T18	386
valid_sources[0x26]	6021	1			T23	2		T15	662		T18	340
valid_sources[0x27]	5036	1			T15	770		T46	1		T18	358
valid_sources[0x28]	4650	1			T23	1		T15	652		T18	329
valid_sources[0x29]	5013	1			T15	633		T18	518		T19	436
valid_sources[0x2a]	5485	1			T20	1		T23	1		T15	676
valid_sources[0x2b]	5754	1			T20	2		T15	628		T62	1
valid_sources[0x2c]	4836	1			T4	1		T15	713		T60	2
valid_sources[0x2d]	4806	1			T23	3		T15	725		T18	301
valid_sources[0x2e]	5028	1			T2	1		T15	666		T18	380
valid_sources[0x2f]	5002	1			T21	2		T15	614		T18	396
valid_sources[0x30]	4541	1			T15	696		T18	347		T19	458
valid_sources[0x31]	5402	1			T15	659		T18	357		T19	499
valid_sources[0x32]	4993	1			T4	1		T30	2		T20	1
valid_sources[0x33]	5388	1			T15	625		T46	1		T18	339
valid_sources[0x34]	4708	1			T15	720		T18	321		T19	468
valid_sources[0x35]	5727	1			T15	776		T62	1		T18	351
valid_sources[0x36]	5161	1			T15	682		T60	1		T18	326
valid_sources[0x37]	4984	1			T3	3		T15	618		T58	1
valid_sources[0x38]	4571	1			T15	666		T18	299		T19	467
valid_sources[0x39]	4883	1			T15	825		T18	359		T19	484
valid_sources[0x3a]	5231	1			T2	3		T21	1		T15	702
valid_sources[0x3b]	4804	1			T15	638		T18	293		T19	490
valid_sources[0x3c]	5404	1			T13	1		T15	702		T59	1
valid_sources[0x3d]	4675	1			T70	1		T15	714		T18	441
valid_sources[0x3e]	5597	1			T15	622		T18	343		T19	468
valid_sources[0x3f]	5618	1			T2	1		T20	1		T15	786
valid_sources[0x40]	4929	1			T15	632		T18	326		T19	449
valid_sources[0x41]	4807	1			T23	1		T15	643		T46	1
valid_sources[0x42]	5658	1			T21	1		T23	1		T15	742
valid_sources[0x43]	5425	1			T15	634		T18	261		T19	484
valid_sources[0x44]	5163	1			T20	2		T15	610		T18	415
valid_sources[0x45]	4367	1			T12	1		T15	697		T18	290
valid_sources[0x46]	5349	1			T15	712		T58	2		T18	328
valid_sources[0x47]	5384	1			T20	1		T15	627		T60	2
valid_sources[0x48]	5890	1			T13	1		T15	768		T18	352
valid_sources[0x49]	5009	1			T3	1		T23	3		T15	623
valid_sources[0x4a]	4735	1			T13	1		T23	7		T15	668
valid_sources[0x4b]	4611	1			T3	2		T15	740		T59	1
valid_sources[0x4c]	5015	1			T15	785		T18	398		T83	1
valid_sources[0x4d]	6201	1			T15	616		T18	288		T19	459
valid_sources[0x4e]	5392	1			T15	642		T18	444		T19	493
valid_sources[0x4f]	5128	1			T4	1		T9	1		T13	1
valid_sources[0x50]	4801	1			T15	637		T18	296		T19	489
valid_sources[0x51]	5313	1			T2	1		T15	666		T18	385
valid_sources[0x52]	5119	1			T21	1		T15	697		T58	1
valid_sources[0x53]	5576	1			T23	3		T15	702		T18	319
valid_sources[0x54]	5889	1			T23	3		T15	638		T46	1
valid_sources[0x55]	4221	1			T23	2		T15	655		T18	283
valid_sources[0x56]	4600	1			T13	1		T15	643		T58	3
valid_sources[0x57]	4559	1			T3	1		T15	647		T18	286
valid_sources[0x58]	4705	1			T23	1		T15	624		T18	271
valid_sources[0x59]	5449	1			T15	711		T18	369		T19	466
valid_sources[0x5a]	5772	1			T15	648		T18	342		T83	2
valid_sources[0x5b]	4892	1			T4	1		T12	1		T15	734
valid_sources[0x5c]	4979	1			T15	680		T18	307		T83	1
valid_sources[0x5d]	5287	1			T13	1		T44	29		T15	721
valid_sources[0x5e]	6011	1			T13	1		T20	1		T15	629
valid_sources[0x5f]	4921	1			T15	731		T60	1		T18	326
valid_sources[0x60]	4983	1			T2	2		T15	718		T46	2
valid_sources[0x61]	4662	1			T13	1		T15	713		T18	317
valid_sources[0x62]	4180	1			T20	1		T15	681		T18	312
valid_sources[0x63]	4586	1			T3	1		T20	1		T23	3
valid_sources[0x64]	4795	1			T3	1		T15	693		T58	5
valid_sources[0x65]	5377	1			T13	1		T15	722		T18	342
valid_sources[0x66]	4489	1			T15	703		T18	237		T19	458
valid_sources[0x67]	5622	1			T15	700		T18	265		T19	487
valid_sources[0x68]	5263	1			T15	702		T60	5		T18	238
valid_sources[0x69]	4913	1			T15	764		T46	1		T18	263
valid_sources[0x6a]	5108	1			T21	1		T15	656		T61	1
valid_sources[0x6b]	5237	1			T15	653		T18	286		T19	483
valid_sources[0x6c]	5419	1			T2	2		T21	2		T23	1
valid_sources[0x6d]	4834	1			T15	630		T18	279		T19	526
valid_sources[0x6e]	5010	1			T15	637		T58	1		T18	301
valid_sources[0x6f]	5355	1			T3	1		T15	610		T18	297
valid_sources[0x70]	4644	1			T21	1		T15	699		T18	318
valid_sources[0x71]	5360	1			T20	1		T23	2		T15	687
valid_sources[0x72]	4613	1			T20	1		T23	9		T15	729
valid_sources[0x73]	5655	1			T21	3		T15	760		T61	1
valid_sources[0x74]	5874	1			T15	626		T26	2		T18	346
valid_sources[0x75]	4922	1			T4	1		T21	1		T23	1
valid_sources[0x76]	4762	1			T13	1		T21	1		T71	1
valid_sources[0x77]	4948	1			T3	1		T21	1		T15	588
valid_sources[0x78]	4733	1			T23	1		T15	651		T18	283
valid_sources[0x79]	4956	1			T23	2		T15	757		T18	296
valid_sources[0x7a]	4836	1			T2	1		T15	715		T45	1
valid_sources[0x7b]	5343	1			T21	1		T23	5		T15	645
valid_sources[0x7c]	5122	1			T21	1		T15	685		T58	2
valid_sources[0x7d]	5960	1			T15	755		T18	291		T83	1
valid_sources[0x7e]	5793	1			T20	1		T15	659		T18	383
valid_sources[0x7f]	5209	1			T2	2		T3	1		T20	1
valid_sources[0x80]	4788	1			T15	699		T18	255		T19	469

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

305001

1

T2

16

T3

16

T6

24

values[0x0]

all_enables

biggest_size

449267

1

T4

2

T10

1

T12

1

values[0x1]

all_enables

biggest_size

447055

1

T10

1

T12

2

T31

1