Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2891050

1

T5

192

T6

51

T7

362

full_word

1845758

1

T2

4

T3

4

T5

21

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4736528	1			T2	4		T3	4		T5	213
auto[TlIntgErrCmd]	96	1			T64	2		T65	6		T66	5
auto[TlIntgErrData]	93	1			T64	3		T66	4		T114	5
auto[TlIntgErrBoth]	91	1			T64	5		T65	4		T66	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

755930

1

T2

4

T3

4

T5

213

auto[1]

3980878

1

T15

526006

T18

264976

T19

346878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	319679	1			T5	192		T6	51		T7	362
auto[TlIntgErrNone]	partial	auto[1]	2571109	1			T15	339504		T18	169208		T19	224392
auto[TlIntgErrNone]	full_word	auto[0]	436128	1			T2	4		T3	4		T5	21
auto[TlIntgErrNone]	full_word	auto[1]	1409612	1			T15	186502		T18	95768		T19	122486
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T64	1		T65	2		T66	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T64	1		T65	4		T66	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T118	1		T119	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T115	1		T120	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T64	1		T66	4		T112	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T64	2		T114	4		T112	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T114	1		T113	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T122	1		T121	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T64	3		T65	2		T114	4
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T64	2		T65	2		T66	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T123	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T115	2		T120	1		-	-