Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3378680

1

T1

63

T2

74

T6

59

full_word

2135369

1

T1

3

T2

7

T6

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5513769	1			T1	66		T2	81		T6	63
auto[TlIntgErrCmd]	88	1			T52	4		T53	5		T54	8
auto[TlIntgErrData]	86	1			T52	2		T53	8		T54	6
auto[TlIntgErrBoth]	106	1			T52	4		T53	7		T54	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870250

1

T1

66

T2

81

T6

63

auto[1]

4643799

1

T12

102445

T13

184788

T14

389921

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	365556	1			T1	63		T2	74		T6	59
auto[TlIntgErrNone]	partial	auto[1]	3012864	1			T12	66814		T13	121531		T14	248248
auto[TlIntgErrNone]	full_word	auto[0]	504576	1			T1	3		T2	7		T6	4
auto[TlIntgErrNone]	full_word	auto[1]	1630773	1			T12	35631		T13	63257		T14	141673
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T52	1		T53	3		T54	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T52	2		T53	2		T54	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T52	1		T109	1		T105	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T110	1		T109	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T52	1		T53	5		T54	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T52	1		T53	2		T54	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T53	1		T102	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T112	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T53	1		T54	2		T99	2
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T52	3		T53	5		T54	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T52	1		T53	1		T99	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T104	1		-	-		-	-