Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2393704

1

T1

154

T3

92

T4

49

full_word

1521351

1

T1

19

T3

9

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3914735	1			T1	173		T3	101		T4	57
auto[TlIntgErrCmd]	118	1			T57	3		T58	4		T59	6
auto[TlIntgErrData]	102	1			T57	4		T58	3		T59	6
auto[TlIntgErrBoth]	100	1			T57	3		T58	3		T59	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626903

1

T1

173

T3

101

T4

57

auto[1]

3288152

1

T12

445604

T13

154563

T14

160557

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	267143	1			T1	154		T3	92		T4	49
auto[TlIntgErrNone]	partial	auto[1]	2126271	1			T12	291232		T13	101534		T14	101634
auto[TlIntgErrNone]	full_word	auto[0]	359622	1			T1	19		T3	9		T4	8
auto[TlIntgErrNone]	full_word	auto[1]	1161699	1			T12	154372		T13	53029		T14	58923
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T58	3		T59	1		T103	3
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T57	3		T58	1		T59	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T59	1		T103	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T103	1		T110	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T57	3		T58	3		T59	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T57	1		T59	3		T103	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T104	1		T108	2		T111	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T110	2		T112	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	27	1			T58	2		T59	3		T103	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T57	2		T58	1		T59	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T57	1		T104	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T108	2		T111	1		T114	1