Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1667360

1

T2

140

T4

61

T5

174

full_word

1090080

1

T2

10

T3

4

T4

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2757140	1			T2	150		T3	4		T4	67
auto[TlIntgErrCmd]	109	1			T53	7		T54	8		T55	4
auto[TlIntgErrData]	99	1			T53	8		T54	8		T55	2
auto[TlIntgErrBoth]	92	1			T53	5		T54	4		T55	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

451281

1

T2

150

T3

4

T4

67

auto[1]

2306159

1

T12

106367

T13

342678

T14

379899

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	192024	1			T2	140		T4	61		T5	174
auto[TlIntgErrNone]	partial	auto[1]	1475068	1			T12	68298		T13	219137		T14	243494
auto[TlIntgErrNone]	full_word	auto[0]	259140	1			T2	10		T3	4		T4	6
auto[TlIntgErrNone]	full_word	auto[1]	830908	1			T12	38069		T13	123541		T14	136405
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T53	3		T54	1		T96	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T53	4		T54	6		T55	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T103	1		T104	1		T105	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T54	1		T98	2		T106	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T53	3		T54	1		T55	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T53	4		T54	7		T55	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T96	1		T100	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T53	1		T99	1		T108	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T53	3		T54	3		T55	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T53	2		T54	1		T55	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T102	2		T109	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T55	2		T100	1		T98	1