Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	75857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1823380

1

T2

17

T3

17

T4

40310

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	496788	1			T2	183		T3	133		T4	10979
values[0x0]	688446	1			T4	15428		T11	29833		T12	49393
values[0x1]	714003	1			T4	15600		T11	31141		T12	51006

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1860011

1

T2

104

T3

79

T4

41153

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6806	1			T3	1		T4	150		T9	1
valid_sources[0x01]	7212	1			T3	1		T4	170		T11	375
valid_sources[0x02]	7421	1			T4	169		T11	339		T97	1
valid_sources[0x03]	7504	1			T4	165		T8	1		T11	311
valid_sources[0x04]	7957	1			T4	178		T11	298		T112	2
valid_sources[0x05]	7121	1			T4	132		T8	1		T11	321
valid_sources[0x06]	7446	1			T4	177		T40	13		T13	5
valid_sources[0x07]	7455	1			T4	162		T11	348		T96	1
valid_sources[0x08]	9477	1			T4	173		T11	296		T95	6
valid_sources[0x09]	7643	1			T4	160		T11	333		T92	3
valid_sources[0x0a]	7166	1			T4	175		T11	325		T97	2
valid_sources[0x0b]	7338	1			T4	164		T11	303		T95	5
valid_sources[0x0c]	7004	1			T3	4		T4	145		T11	345
valid_sources[0x0d]	6890	1			T3	1		T4	184		T11	303
valid_sources[0x0e]	6981	1			T4	171		T11	310		T95	7
valid_sources[0x0f]	7012	1			T4	145		T11	310		T92	1
valid_sources[0x10]	7150	1			T4	174		T6	10		T11	331
valid_sources[0x11]	7965	1			T4	152		T11	330		T96	4
valid_sources[0x12]	7255	1			T3	3		T4	150		T11	347
valid_sources[0x13]	7592	1			T3	1		T4	139		T11	317
valid_sources[0x14]	6918	1			T4	151		T6	13		T8	1
valid_sources[0x15]	7243	1			T3	1		T4	149		T11	309
valid_sources[0x16]	7095	1			T4	179		T11	289		T96	1
valid_sources[0x17]	7120	1			T4	171		T13	26		T11	292
valid_sources[0x18]	7674	1			T4	163		T8	1		T11	300
valid_sources[0x19]	7812	1			T2	20		T4	163		T11	317
valid_sources[0x1a]	7360	1			T4	176		T6	14		T11	329
valid_sources[0x1b]	7640	1			T4	138		T11	321		T95	1
valid_sources[0x1c]	7525	1			T4	157		T8	1		T11	315
valid_sources[0x1d]	7869	1			T4	177		T40	15		T11	290
valid_sources[0x1e]	7925	1			T4	156		T6	17		T11	313
valid_sources[0x1f]	7608	1			T4	194		T11	333		T42	2
valid_sources[0x20]	7457	1			T4	156		T11	314		T95	7
valid_sources[0x21]	7907	1			T4	190		T8	1		T11	346
valid_sources[0x22]	8161	1			T3	1		T4	177		T11	306
valid_sources[0x23]	8374	1			T3	1		T4	170		T11	339
valid_sources[0x24]	7474	1			T3	2		T4	165		T11	342
valid_sources[0x25]	6849	1			T4	170		T11	307		T95	4
valid_sources[0x26]	7619	1			T3	1		T4	157		T13	5
valid_sources[0x27]	7176	1			T4	170		T11	346		T97	2
valid_sources[0x28]	8756	1			T4	179		T11	305		T95	6
valid_sources[0x29]	7941	1			T3	1		T4	165		T15	1
valid_sources[0x2a]	8134	1			T4	184		T14	1		T11	300
valid_sources[0x2b]	7647	1			T4	194		T11	344		T92	1
valid_sources[0x2c]	8012	1			T3	2		T4	171		T11	333
valid_sources[0x2d]	7618	1			T4	157		T11	326		T68	6
valid_sources[0x2e]	7077	1			T4	156		T8	1		T11	319
valid_sources[0x2f]	7122	1			T4	130		T8	2		T11	340
valid_sources[0x30]	7814	1			T4	166		T40	19		T11	310
valid_sources[0x31]	7403	1			T2	35		T4	175		T11	320
valid_sources[0x32]	7152	1			T4	153		T8	1		T11	302
valid_sources[0x33]	7276	1			T4	174		T8	1		T11	316
valid_sources[0x34]	7381	1			T4	142		T11	321		T97	1
valid_sources[0x35]	7045	1			T4	186		T11	327		T96	3
valid_sources[0x36]	7378	1			T4	203		T11	324		T95	1
valid_sources[0x37]	7145	1			T3	2		T4	175		T11	359
valid_sources[0x38]	7462	1			T3	1		T4	156		T11	315
valid_sources[0x39]	7197	1			T3	1		T4	175		T11	324
valid_sources[0x3a]	6811	1			T3	2		T4	169		T11	315
valid_sources[0x3b]	7532	1			T4	164		T13	3		T11	328
valid_sources[0x3c]	8536	1			T4	140		T11	316		T95	2
valid_sources[0x3d]	7415	1			T4	168		T13	1		T11	323
valid_sources[0x3e]	7781	1			T4	157		T11	305		T95	2
valid_sources[0x3f]	7428	1			T4	154		T11	289		T96	3
valid_sources[0x40]	7102	1			T4	175		T11	338		T42	3
valid_sources[0x41]	7076	1			T3	1		T4	155		T13	8
valid_sources[0x42]	7251	1			T4	157		T11	348		T96	2
valid_sources[0x43]	7263	1			T4	156		T8	2		T9	1
valid_sources[0x44]	8230	1			T3	2		T4	157		T11	302
valid_sources[0x45]	7442	1			T3	1		T4	180		T11	293
valid_sources[0x46]	7040	1			T3	2		T4	174		T11	319
valid_sources[0x47]	7016	1			T4	152		T11	283		T95	1
valid_sources[0x48]	8247	1			T4	192		T10	1		T34	1
valid_sources[0x49]	7098	1			T4	158		T13	2		T11	323
valid_sources[0x4a]	7479	1			T4	167		T11	322		T96	4
valid_sources[0x4b]	7075	1			T4	161		T8	2		T11	336
valid_sources[0x4c]	7228	1			T4	180		T11	278		T94	8
valid_sources[0x4d]	7352	1			T4	194		T11	324		T12	537
valid_sources[0x4e]	7092	1			T2	13		T4	160		T40	29
valid_sources[0x4f]	7318	1			T4	185		T10	6		T11	324
valid_sources[0x50]	7208	1			T4	158		T11	322		T95	2
valid_sources[0x51]	6961	1			T4	156		T11	303		T96	1
valid_sources[0x52]	7127	1			T4	172		T11	317		T95	3
valid_sources[0x53]	7263	1			T4	161		T11	327		T95	3
valid_sources[0x54]	8189	1			T4	172		T8	4		T11	332
valid_sources[0x55]	7039	1			T4	177		T11	318		T92	3
valid_sources[0x56]	7108	1			T4	152		T8	4		T11	292
valid_sources[0x57]	8175	1			T4	162		T11	338		T68	5
valid_sources[0x58]	7075	1			T3	1		T4	168		T11	274
valid_sources[0x59]	7339	1			T4	187		T11	299		T12	547
valid_sources[0x5a]	7086	1			T4	170		T8	3		T13	2
valid_sources[0x5b]	7712	1			T3	2		T4	160		T11	328
valid_sources[0x5c]	7859	1			T4	193		T11	351		T68	2
valid_sources[0x5d]	6961	1			T3	1		T4	186		T11	317
valid_sources[0x5e]	6836	1			T4	160		T11	318		T92	2
valid_sources[0x5f]	7544	1			T4	178		T11	299		T94	9
valid_sources[0x60]	7027	1			T4	148		T8	2		T14	5
valid_sources[0x61]	7837	1			T3	5		T4	182		T9	1
valid_sources[0x62]	8272	1			T4	210		T11	335		T42	1
valid_sources[0x63]	7605	1			T3	4		T4	175		T11	312
valid_sources[0x64]	7622	1			T4	139		T13	4		T11	341
valid_sources[0x65]	7852	1			T4	155		T8	1		T11	319
valid_sources[0x66]	7657	1			T3	1		T4	180		T8	1
valid_sources[0x67]	7401	1			T3	4		T4	174		T11	322
valid_sources[0x68]	7156	1			T3	2		T4	161		T11	315
valid_sources[0x69]	7038	1			T4	142		T13	1		T11	292
valid_sources[0x6a]	7115	1			T4	152		T8	2		T11	326
valid_sources[0x6b]	7524	1			T2	22		T3	1		T4	160
valid_sources[0x6c]	7136	1			T4	152		T11	316		T92	1
valid_sources[0x6d]	7234	1			T3	1		T4	180		T11	315
valid_sources[0x6e]	7117	1			T4	147		T11	327		T97	1
valid_sources[0x6f]	7728	1			T4	164		T11	304		T96	4
valid_sources[0x70]	7742	1			T4	148		T8	2		T11	328
valid_sources[0x71]	7013	1			T4	170		T11	316		T95	4
valid_sources[0x72]	7173	1			T4	152		T11	271		T12	536
valid_sources[0x73]	7343	1			T4	156		T11	312		T92	1
valid_sources[0x74]	7122	1			T4	161		T11	324		T95	2
valid_sources[0x75]	6948	1			T4	196		T8	1		T11	330
valid_sources[0x76]	7247	1			T4	175		T5	1		T11	316
valid_sources[0x77]	7122	1			T4	172		T11	321		T95	1
valid_sources[0x78]	6877	1			T4	163		T8	1		T40	28
valid_sources[0x79]	7214	1			T4	155		T11	322		T94	6
valid_sources[0x7a]	7724	1			T4	194		T8	2		T11	321
valid_sources[0x7b]	7422	1			T4	155		T11	286		T12	536
valid_sources[0x7c]	7732	1			T4	165		T11	319		T12	536
valid_sources[0x7d]	7813	1			T3	1		T4	171		T11	348
valid_sources[0x7e]	7362	1			T4	151		T11	311		T95	2
valid_sources[0x7f]	7067	1			T4	143		T13	1		T11	312
valid_sources[0x80]	7344	1			T4	169		T11	336		T92	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

458831

1

T2

17

T3

17

T4

10047

values[0x0]

all_enables

biggest_size

682236

1

T4

15313

T11

29537

T12

48912

values[0x1]

all_enables

biggest_size

682313

1

T4

14950

T11

29693

T12

48783

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	137974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1402583

1

T1

3

T3

23

T4

32045

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	385505	1			T3	64		T4	8943		T5	26
values[0x0]	535432	1			T1	5		T4	12220		T7	6
values[0x1]	619620	1			T1	3		T4	13855		T7	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1478265

1

T1

3

T3

33

T4

33684

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6678	1			T4	122		T12	438		T46	327
valid_sources[0x01]	6009	1			T3	2		T4	122		T11	376
valid_sources[0x02]	5448	1			T4	141		T13	1		T11	809
valid_sources[0x03]	5097	1			T4	131		T11	200		T12	238
valid_sources[0x04]	6867	1			T4	135		T11	438		T12	802
valid_sources[0x05]	6453	1			T4	152		T8	1		T10	1
valid_sources[0x06]	7102	1			T3	2		T4	140		T11	346
valid_sources[0x07]	5195	1			T4	118		T6	2		T13	1
valid_sources[0x08]	7292	1			T4	119		T11	672		T12	356
valid_sources[0x09]	6913	1			T3	1		T4	154		T34	4
valid_sources[0x0a]	5447	1			T4	137		T5	3		T13	1
valid_sources[0x0b]	5312	1			T4	142		T11	8		T12	209
valid_sources[0x0c]	6348	1			T4	131		T11	393		T12	741
valid_sources[0x0d]	6760	1			T4	141		T11	216		T94	3
valid_sources[0x0e]	6637	1			T3	1		T4	146		T11	685
valid_sources[0x0f]	4932	1			T3	1		T4	132		T6	2
valid_sources[0x10]	5348	1			T3	1		T4	148		T11	117
valid_sources[0x11]	7307	1			T4	127		T7	5		T11	854
valid_sources[0x12]	5572	1			T4	133		T11	3		T12	298
valid_sources[0x13]	6568	1			T4	157		T12	539		T46	272
valid_sources[0x14]	6120	1			T4	141		T13	3		T11	189
valid_sources[0x15]	6928	1			T4	146		T13	1		T11	366
valid_sources[0x16]	5466	1			T4	145		T11	120		T12	611
valid_sources[0x17]	5472	1			T1	1		T3	1		T4	154
valid_sources[0x18]	6457	1			T4	148		T11	294		T12	97
valid_sources[0x19]	6797	1			T4	132		T6	1		T11	414
valid_sources[0x1a]	6396	1			T4	137		T11	193		T94	3
valid_sources[0x1b]	6090	1			T3	1		T4	141		T11	1
valid_sources[0x1c]	5478	1			T4	106		T15	17		T11	1
valid_sources[0x1d]	5077	1			T4	153		T10	1		T13	1
valid_sources[0x1e]	7864	1			T4	133		T13	1		T11	885
valid_sources[0x1f]	5785	1			T3	1		T4	140		T12	434
valid_sources[0x20]	6454	1			T4	137		T8	1		T11	623
valid_sources[0x21]	3996	1			T3	1		T4	144		T12	244
valid_sources[0x22]	6417	1			T4	139		T13	2		T11	159
valid_sources[0x23]	6756	1			T4	140		T6	7		T11	104
valid_sources[0x24]	6263	1			T4	148		T11	617		T12	311
valid_sources[0x25]	5356	1			T4	123		T11	17		T92	2
valid_sources[0x26]	6653	1			T4	131		T11	936		T12	653
valid_sources[0x27]	5943	1			T4	126		T11	471		T59	14
valid_sources[0x28]	5415	1			T4	143		T6	3		T11	396
valid_sources[0x29]	5985	1			T3	1		T4	138		T92	1
valid_sources[0x2a]	5895	1			T3	2		T4	152		T11	20
valid_sources[0x2b]	5606	1			T1	1		T4	133		T13	1
valid_sources[0x2c]	6015	1			T4	141		T11	100		T12	588
valid_sources[0x2d]	5663	1			T4	140		T11	82		T94	1
valid_sources[0x2e]	5943	1			T3	1		T4	146		T11	132
valid_sources[0x2f]	6087	1			T3	1		T4	114		T6	2
valid_sources[0x30]	6555	1			T4	134		T13	1		T11	398
valid_sources[0x31]	6377	1			T4	139		T8	1		T11	141
valid_sources[0x32]	4993	1			T4	113		T11	19		T12	113
valid_sources[0x33]	5993	1			T4	153		T11	375		T12	459
valid_sources[0x34]	5727	1			T4	146		T11	381		T12	647
valid_sources[0x35]	6436	1			T4	125		T13	2		T12	611
valid_sources[0x36]	7182	1			T3	1		T4	150		T34	2
valid_sources[0x37]	6055	1			T4	133		T11	374		T12	363
valid_sources[0x38]	6527	1			T4	135		T13	1		T11	797
valid_sources[0x39]	5400	1			T4	158		T13	1		T11	5
valid_sources[0x3a]	6817	1			T4	137		T11	610		T12	440
valid_sources[0x3b]	6086	1			T3	2		T4	128		T5	2
valid_sources[0x3c]	6877	1			T4	147		T13	2		T11	626
valid_sources[0x3d]	6130	1			T4	128		T8	1		T13	1
valid_sources[0x3e]	7278	1			T4	136		T11	398		T12	375
valid_sources[0x3f]	6124	1			T4	143		T8	2		T11	509
valid_sources[0x40]	5705	1			T4	142		T5	3		T11	211
valid_sources[0x41]	5591	1			T3	1		T4	117		T13	2
valid_sources[0x42]	5992	1			T4	104		T11	107		T12	454
valid_sources[0x43]	5383	1			T4	127		T34	3		T11	3
valid_sources[0x44]	6823	1			T4	131		T11	90		T92	1
valid_sources[0x45]	7308	1			T4	137		T13	2		T11	71
valid_sources[0x46]	6388	1			T4	134		T11	419		T92	1
valid_sources[0x47]	6901	1			T4	129		T11	441		T12	384
valid_sources[0x48]	5608	1			T3	1		T4	157		T11	206
valid_sources[0x49]	6067	1			T4	142		T11	86		T12	262
valid_sources[0x4a]	6287	1			T4	130		T11	170		T12	819
valid_sources[0x4b]	6184	1			T4	135		T11	285		T12	140
valid_sources[0x4c]	6887	1			T4	115		T11	370		T12	517
valid_sources[0x4d]	6151	1			T4	98		T5	1		T7	6
valid_sources[0x4e]	6254	1			T3	1		T4	146		T6	1
valid_sources[0x4f]	5956	1			T4	164		T11	8		T92	1
valid_sources[0x50]	5606	1			T4	145		T11	104		T12	156
valid_sources[0x51]	5494	1			T4	135		T11	413		T94	1
valid_sources[0x52]	5465	1			T4	141		T13	1		T11	168
valid_sources[0x53]	7420	1			T3	1		T4	127		T11	413
valid_sources[0x54]	5597	1			T4	133		T5	3		T11	7
valid_sources[0x55]	6863	1			T3	1		T4	130		T11	657
valid_sources[0x56]	6250	1			T1	3		T3	1		T4	123
valid_sources[0x57]	6873	1			T3	2		T4	154		T8	1
valid_sources[0x58]	4795	1			T4	141		T11	236		T12	161
valid_sources[0x59]	5833	1			T3	2		T4	115		T10	1
valid_sources[0x5a]	6554	1			T4	152		T6	1		T11	322
valid_sources[0x5b]	5440	1			T4	126		T11	317		T12	355
valid_sources[0x5c]	5826	1			T4	148		T11	624		T12	173
valid_sources[0x5d]	6271	1			T4	138		T11	154		T94	1
valid_sources[0x5e]	4880	1			T4	127		T11	162		T94	1
valid_sources[0x5f]	4801	1			T4	147		T8	1		T11	160
valid_sources[0x60]	4906	1			T4	146		T11	118		T12	168
valid_sources[0x61]	6034	1			T4	148		T11	859		T12	247
valid_sources[0x62]	7278	1			T4	157		T11	519		T94	1
valid_sources[0x63]	6494	1			T4	132		T11	290		T12	838
valid_sources[0x64]	5005	1			T4	147		T11	467		T12	431
valid_sources[0x65]	6236	1			T4	136		T11	501		T12	225
valid_sources[0x66]	7392	1			T4	130		T11	97		T12	1045
valid_sources[0x67]	5707	1			T4	137		T13	1		T11	91
valid_sources[0x68]	5476	1			T3	1		T4	130		T11	242
valid_sources[0x69]	7039	1			T4	112		T11	554		T12	452
valid_sources[0x6a]	5482	1			T4	138		T11	274		T12	990
valid_sources[0x6b]	5233	1			T3	1		T4	147		T8	1
valid_sources[0x6c]	6833	1			T4	135		T8	1		T10	1
valid_sources[0x6d]	6826	1			T4	128		T11	441		T12	59
valid_sources[0x6e]	6580	1			T4	140		T6	1		T11	2
valid_sources[0x6f]	7193	1			T3	1		T4	134		T13	1
valid_sources[0x70]	6672	1			T3	1		T4	127		T11	16
valid_sources[0x71]	5638	1			T4	139		T13	1		T11	515
valid_sources[0x72]	6187	1			T4	126		T11	805		T12	248
valid_sources[0x73]	5654	1			T4	151		T13	1		T11	423
valid_sources[0x74]	4714	1			T3	1		T4	124		T5	1
valid_sources[0x75]	6999	1			T4	142		T5	1		T7	2
valid_sources[0x76]	5089	1			T4	142		T13	1		T11	8
valid_sources[0x77]	5818	1			T4	133		T11	393		T12	631
valid_sources[0x78]	6008	1			T4	138		T11	360		T12	102
valid_sources[0x79]	6737	1			T4	135		T8	1		T13	1
valid_sources[0x7a]	5211	1			T4	139		T11	4		T12	62
valid_sources[0x7b]	6108	1			T4	139		T8	1		T11	275
valid_sources[0x7c]	5469	1			T4	123		T5	2		T11	30
valid_sources[0x7d]	4361	1			T4	138		T11	3		T94	1
valid_sources[0x7e]	6887	1			T3	2		T4	143		T11	669
valid_sources[0x7f]	6573	1			T3	1		T4	137		T11	114
valid_sources[0x80]	5293	1			T4	122		T11	2		T12	154

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

354622

1

T3

23

T4

8260

T5

16

values[0x0]

all_enables

biggest_size

524488

1

T1

1

T4

11986

T7

3

values[0x1]

all_enables

biggest_size

523473

1

T1

2

T4

11799

T7

3