Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3365374

1

T2

166

T3

116

T4

75889

full_word

2130961

1

T2

17

T3

17

T4

47308

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5496025	1			T2	183		T3	133		T4	123197
auto[TlIntgErrCmd]	101	1			T52	4		T53	6		T54	6
auto[TlIntgErrData]	105	1			T52	7		T53	3		T54	3
auto[TlIntgErrBoth]	104	1			T52	9		T53	1		T54	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870378

1

T2

183

T3

133

T4

19773

auto[1]

4625957

1

T4

103424

T11

207526

T12

336406

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	367070	1			T2	166		T3	116		T4	8676
auto[TlIntgErrNone]	partial	auto[1]	2998021	1			T4	67213		T11	136441		T12	219288
auto[TlIntgErrNone]	full_word	auto[0]	503161	1			T2	17		T3	17		T4	11097
auto[TlIntgErrNone]	full_word	auto[1]	1627773	1			T4	36211		T11	71085		T12	117118
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T52	1		T53	2		T54	4
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T52	2		T53	4		T54	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T101	1		T104	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T52	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	57	1			T52	3		T53	3		T54	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T52	3		T54	1		T100	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T100	1		T107	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T52	1		T106	1		T103	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T52	3		T54	1		T100	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T52	6		T53	1		T100	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T101	1		T107	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T101	1		T106	1		T103	1