Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 58507 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1450720 1 T2 9 T3 3 T4 10



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 392604 1 T2 90 T3 3 T4 69
values[0x0] 547897 1 T15 62073 T16 14582 T17 63518
values[0x1] 568726 1 T15 64684 T16 15105 T17 65725



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 30320 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1478907 1 T2 55 T3 3 T4 39



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 5978 1 T7 1 T43 3 T110 39
valid_sources[0x01] 5350 1 T19 1 T43 4 T39 1
valid_sources[0x02] 5226 1 T6 2 T7 5 T15 3
valid_sources[0x03] 6199 1 T112 2 T12 34 T15 861
valid_sources[0x04] 6595 1 T6 1 T64 2 T14 1
valid_sources[0x05] 6445 1 T112 1 T111 5 T114 18
valid_sources[0x06] 6736 1 T7 12 T43 2 T64 1
valid_sources[0x07] 5279 1 T43 1 T64 1 T114 3
valid_sources[0x08] 5341 1 T10 5 T19 1 T15 122
valid_sources[0x09] 5460 1 T7 3 T8 4 T18 11
valid_sources[0x0a] 5551 1 T18 8 T19 1 T31 1
valid_sources[0x0b] 6571 1 T7 1 T19 1 T43 4
valid_sources[0x0c] 5448 1 T2 13 T114 3 T15 329
valid_sources[0x0d] 5620 1 T5 1 T8 2 T19 1
valid_sources[0x0e] 6307 1 T43 2 T112 1 T14 2
valid_sources[0x0f] 5203 1 T43 2 T78 11 T15 6
valid_sources[0x10] 5320 1 T64 2 T112 1 T31 1
valid_sources[0x11] 6089 1 T7 2 T18 2 T19 2
valid_sources[0x12] 7258 1 T7 1 T112 1 T14 1
valid_sources[0x13] 5710 1 T10 5 T43 1 T114 4
valid_sources[0x14] 6180 1 T78 12 T114 6 T31 1
valid_sources[0x15] 6114 1 T7 2 T112 1 T15 897
valid_sources[0x16] 5512 1 T18 4 T112 2 T31 3
valid_sources[0x17] 5497 1 T7 2 T19 1 T110 22
valid_sources[0x18] 6116 1 T19 2 T43 1 T64 3
valid_sources[0x19] 5781 1 T19 1 T43 1 T15 526
valid_sources[0x1a] 5880 1 T112 2 T114 3 T14 1
valid_sources[0x1b] 5291 1 T78 2 T15 183 T16 167
valid_sources[0x1c] 5479 1 T19 1 T111 5 T31 7
valid_sources[0x1d] 6122 1 T15 755 T16 191 T129 4
valid_sources[0x1e] 6080 1 T8 4 T10 14 T64 1
valid_sources[0x1f] 5702 1 T43 1 T112 1 T78 9
valid_sources[0x20] 5865 1 T7 10 T19 2 T14 4
valid_sources[0x21] 5335 1 T7 5 T16 159 T130 1
valid_sources[0x22] 5064 1 T6 2 T7 2 T19 1
valid_sources[0x23] 7047 1 T11 16 T112 1 T111 1
valid_sources[0x24] 6473 1 T7 2 T112 2 T111 1
valid_sources[0x25] 5976 1 T2 29 T4 2 T7 1
valid_sources[0x26] 5897 1 T43 6 T15 952 T131 2
valid_sources[0x27] 5484 1 T5 1 T7 2 T19 1
valid_sources[0x28] 5437 1 T13 17 T15 215 T16 161
valid_sources[0x29] 6896 1 T18 6 T114 4 T14 1
valid_sources[0x2a] 7049 1 T43 1 T14 3 T15 1709
valid_sources[0x2b] 5967 1 T6 2 T7 1 T43 1
valid_sources[0x2c] 7044 1 T15 1695 T34 1 T16 168
valid_sources[0x2d] 5741 1 T4 1 T8 1 T19 1
valid_sources[0x2e] 5712 1 T112 1 T15 488 T34 2
valid_sources[0x2f] 5625 1 T7 3 T8 4 T19 1
valid_sources[0x30] 5447 1 T112 1 T15 369 T34 1
valid_sources[0x31] 5742 1 T8 2 T18 7 T11 33
valid_sources[0x32] 5660 1 T4 2 T6 2 T8 1
valid_sources[0x33] 5550 1 T5 1 T64 1 T38 1
valid_sources[0x34] 6404 1 T7 4 T8 1 T43 1
valid_sources[0x35] 6225 1 T43 2 T11 23 T78 18
valid_sources[0x36] 5996 1 T18 2 T43 1 T112 1
valid_sources[0x37] 5247 1 T6 3 T8 2 T43 1
valid_sources[0x38] 6025 1 T31 3 T15 867 T16 165
valid_sources[0x39] 5676 1 T7 7 T43 1 T15 369
valid_sources[0x3a] 6006 1 T7 2 T10 10 T43 2
valid_sources[0x3b] 5455 1 T4 2 T10 15 T18 8
valid_sources[0x3c] 6072 1 T7 5 T78 3 T15 818
valid_sources[0x3d] 5883 1 T8 1 T18 15 T64 3
valid_sources[0x3e] 5737 1 T7 7 T8 1 T43 1
valid_sources[0x3f] 6683 1 T10 10 T19 1 T15 1289
valid_sources[0x40] 5134 1 T10 19 T19 2 T14 1
valid_sources[0x41] 5789 1 T5 1 T6 3 T7 2
valid_sources[0x42] 5136 1 T64 5 T15 64 T34 2
valid_sources[0x43] 5555 1 T10 4 T112 1 T14 1
valid_sources[0x44] 5539 1 T112 3 T114 3 T14 1
valid_sources[0x45] 5687 1 T43 3 T14 1 T15 354
valid_sources[0x46] 6260 1 T7 2 T14 1 T15 1039
valid_sources[0x47] 5194 1 T10 8 T19 1 T78 12
valid_sources[0x48] 5737 1 T10 3 T43 1 T78 19
valid_sources[0x49] 6906 1 T5 1 T114 6 T14 1
valid_sources[0x4a] 5202 1 T19 1 T112 2 T78 11
valid_sources[0x4b] 5404 1 T43 1 T112 2 T15 217
valid_sources[0x4c] 5535 1 T6 2 T43 2 T15 263
valid_sources[0x4d] 5640 1 T10 3 T19 2 T111 2
valid_sources[0x4e] 5684 1 T4 1 T111 2 T15 589
valid_sources[0x4f] 5391 1 T7 10 T19 1 T31 1
valid_sources[0x50] 5152 1 T19 1 T78 5 T14 1
valid_sources[0x51] 6944 1 T8 2 T78 6 T15 1868
valid_sources[0x52] 5507 1 T8 1 T43 2 T14 1
valid_sources[0x53] 6555 1 T18 8 T43 1 T15 1326
valid_sources[0x54] 5715 1 T112 1 T15 480 T16 163
valid_sources[0x55] 5579 1 T5 1 T6 2 T7 1
valid_sources[0x56] 5414 1 T64 3 T78 4 T15 132
valid_sources[0x57] 7133 1 T7 12 T8 1 T15 1868
valid_sources[0x58] 5300 1 T8 1 T43 4 T31 2
valid_sources[0x59] 5632 1 T4 5 T19 1 T43 1
valid_sources[0x5a] 5527 1 T43 3 T64 4 T15 322
valid_sources[0x5b] 6115 1 T8 3 T43 1 T114 3
valid_sources[0x5c] 6233 1 T8 3 T18 1 T78 1
valid_sources[0x5d] 6147 1 T43 2 T78 5 T14 1
valid_sources[0x5e] 5497 1 T7 4 T43 1 T14 1
valid_sources[0x5f] 5382 1 T7 2 T19 1 T112 1
valid_sources[0x60] 5405 1 T43 1 T14 1 T15 318
valid_sources[0x61] 5591 1 T6 2 T18 4 T112 3
valid_sources[0x62] 5570 1 T8 3 T18 13 T14 1
valid_sources[0x63] 5858 1 T19 1 T43 2 T114 9
valid_sources[0x64] 5761 1 T8 1 T19 1 T43 2
valid_sources[0x65] 6582 1 T64 8 T15 1363 T37 1
valid_sources[0x66] 5334 1 T6 3 T7 4 T43 3
valid_sources[0x67] 5246 1 T4 1 T15 332 T34 1
valid_sources[0x68] 5461 1 T2 9 T10 1 T19 1
valid_sources[0x69] 5843 1 T43 1 T64 7 T114 1
valid_sources[0x6a] 6434 1 T10 1 T43 1 T78 2
valid_sources[0x6b] 5906 1 T19 1 T112 3 T14 1
valid_sources[0x6c] 5785 1 T6 3 T43 6 T110 16
valid_sources[0x6d] 5529 1 T112 1 T15 99 T131 2
valid_sources[0x6e] 6317 1 T7 1 T19 2 T21 1
valid_sources[0x6f] 5527 1 T6 3 T7 3 T78 2
valid_sources[0x70] 6565 1 T18 4 T112 3 T114 3
valid_sources[0x71] 5611 1 T10 7 T43 1 T11 30
valid_sources[0x72] 5613 1 T43 1 T111 3 T114 2
valid_sources[0x73] 5357 1 T43 1 T112 1 T14 1
valid_sources[0x74] 6001 1 T8 2 T10 1 T111 2
valid_sources[0x75] 5444 1 T4 13 T7 1 T19 1
valid_sources[0x76] 5947 1 T7 3 T8 1 T114 6
valid_sources[0x77] 5145 1 T8 1 T43 2 T111 1
valid_sources[0x78] 6047 1 T43 1 T64 6 T112 2
valid_sources[0x79] 6263 1 T19 1 T43 1 T114 3
valid_sources[0x7a] 7867 1 T6 2 T8 2 T19 1
valid_sources[0x7b] 6461 1 T8 1 T114 33 T15 988
valid_sources[0x7c] 5574 1 T19 2 T43 2 T30 10
valid_sources[0x7d] 6403 1 T6 2 T64 1 T14 1
valid_sources[0x7e] 5712 1 T19 1 T15 71 T60 5
valid_sources[0x7f] 5305 1 T10 3 T112 1 T34 1
valid_sources[0x80] 6574 1 T10 9 T43 1 T112 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 364424 1 T2 9 T3 3 T4 10
values[0x0] all_enables biggest_size 543040 1 T15 61566 T16 14464 T17 62940
values[0x1] all_enables biggest_size 543256 1 T15 61797 T16 14440 T17 62784


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 108564 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1125928 1 T1 1 T2 17 T3 12



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 308274 1 T2 32 T3 16 T4 32
values[0x0] 429753 1 T1 4 T9 7 T25 4
values[0x1] 496465 1 T1 2 T9 6 T25 6



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 48520 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1185972 1 T1 2 T2 22 T3 13



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4380 1 T11 1 T15 490 T60 1
valid_sources[0x01] 5120 1 T11 1 T15 498 T35 2
valid_sources[0x02] 4351 1 T6 1 T15 539 T16 78
valid_sources[0x03] 4976 1 T19 1 T15 533 T36 2
valid_sources[0x04] 4254 1 T7 2 T12 1 T15 533
valid_sources[0x05] 4853 1 T2 2 T8 1 T15 526
valid_sources[0x06] 5223 1 T11 1 T12 1 T15 542
valid_sources[0x07] 4986 1 T15 508 T16 104 T132 1
valid_sources[0x08] 4073 1 T7 1 T15 511 T16 122
valid_sources[0x09] 5017 1 T15 540 T16 181 T81 1
valid_sources[0x0a] 5290 1 T15 531 T16 172 T133 1
valid_sources[0x0b] 4836 1 T12 2 T15 533 T16 283
valid_sources[0x0c] 4838 1 T7 2 T12 1 T39 1
valid_sources[0x0d] 4252 1 T110 2 T15 528 T36 1
valid_sources[0x0e] 4882 1 T78 5 T31 1 T15 523
valid_sources[0x0f] 4505 1 T7 1 T43 1 T15 553
valid_sources[0x10] 4890 1 T19 1 T78 2 T15 503
valid_sources[0x11] 5545 1 T15 530 T16 80 T40 1
valid_sources[0x12] 4490 1 T21 3 T110 1 T15 491
valid_sources[0x13] 4485 1 T7 1 T15 549 T37 1
valid_sources[0x14] 4583 1 T78 2 T22 2 T15 583
valid_sources[0x15] 5279 1 T7 1 T110 1 T12 1
valid_sources[0x16] 4480 1 T11 1 T39 1 T15 510
valid_sources[0x17] 4462 1 T19 1 T11 1 T15 510
valid_sources[0x18] 4397 1 T43 1 T12 3 T15 511
valid_sources[0x19] 5289 1 T2 2 T4 1 T15 544
valid_sources[0x1a] 4753 1 T8 1 T19 1 T15 572
valid_sources[0x1b] 4968 1 T43 1 T15 547 T37 1
valid_sources[0x1c] 4745 1 T15 497 T16 155 T66 1
valid_sources[0x1d] 5265 1 T15 529 T16 156 T66 1
valid_sources[0x1e] 5173 1 T43 1 T15 482 T16 133
valid_sources[0x1f] 4598 1 T7 1 T110 1 T78 1
valid_sources[0x20] 4596 1 T7 1 T43 1 T78 2
valid_sources[0x21] 5156 1 T7 1 T15 522 T16 111
valid_sources[0x22] 4704 1 T43 2 T15 556 T58 1
valid_sources[0x23] 5696 1 T15 523 T16 257 T81 2
valid_sources[0x24] 4940 1 T7 1 T110 1 T15 555
valid_sources[0x25] 4729 1 T7 1 T39 1 T15 562
valid_sources[0x26] 3882 1 T2 1 T15 501 T16 126
valid_sources[0x27] 5850 1 T7 1 T20 1 T12 1
valid_sources[0x28] 4915 1 T7 1 T15 495 T16 240
valid_sources[0x29] 5101 1 T7 1 T19 1 T43 1
valid_sources[0x2a] 6016 1 T6 1 T78 1 T15 531
valid_sources[0x2b] 5555 1 T43 2 T15 545 T16 87
valid_sources[0x2c] 4138 1 T43 1 T110 2 T15 501
valid_sources[0x2d] 4167 1 T7 1 T15 536 T37 2
valid_sources[0x2e] 6589 1 T19 1 T110 1 T15 549
valid_sources[0x2f] 4484 1 T78 1 T15 532 T36 2
valid_sources[0x30] 4950 1 T2 1 T43 1 T110 2
valid_sources[0x31] 4694 1 T11 2 T15 529 T16 156
valid_sources[0x32] 4737 1 T11 1 T15 546 T37 1
valid_sources[0x33] 4587 1 T7 1 T11 2 T15 550
valid_sources[0x34] 5027 1 T43 1 T15 525 T16 110
valid_sources[0x35] 4991 1 T7 1 T39 1 T15 512
valid_sources[0x36] 4380 1 T43 1 T15 510 T16 41
valid_sources[0x37] 4990 1 T15 541 T16 145 T134 1
valid_sources[0x38] 3761 1 T2 1 T15 557 T36 1
valid_sources[0x39] 5106 1 T6 2 T18 64 T11 1
valid_sources[0x3a] 4132 1 T7 1 T15 544 T16 117
valid_sources[0x3b] 4911 1 T15 571 T37 1 T16 71
valid_sources[0x3c] 4240 1 T43 1 T11 3 T22 1
valid_sources[0x3d] 4189 1 T110 1 T12 1 T15 517
valid_sources[0x3e] 4448 1 T7 3 T8 1 T39 1
valid_sources[0x3f] 4288 1 T12 2 T15 502 T36 1
valid_sources[0x40] 4327 1 T7 1 T31 1 T15 596
valid_sources[0x41] 4995 1 T15 506 T16 162 T23 1
valid_sources[0x42] 4269 1 T7 1 T31 1 T15 494
valid_sources[0x43] 4870 1 T15 497 T16 80 T45 1
valid_sources[0x44] 4908 1 T19 1 T21 2 T15 489
valid_sources[0x45] 5044 1 T7 2 T8 1 T19 1
valid_sources[0x46] 4604 1 T1 1 T7 2 T110 1
valid_sources[0x47] 4623 1 T2 2 T7 1 T11 2
valid_sources[0x48] 4753 1 T8 1 T11 1 T15 514
valid_sources[0x49] 4873 1 T11 3 T110 1 T15 527
valid_sources[0x4a] 4066 1 T11 2 T110 1 T15 496
valid_sources[0x4b] 4198 1 T3 16 T8 1 T19 1
valid_sources[0x4c] 4930 1 T2 2 T78 4 T15 548
valid_sources[0x4d] 3831 1 T15 495 T16 22 T17 241
valid_sources[0x4e] 4845 1 T15 571 T16 216 T82 5
valid_sources[0x4f] 5360 1 T4 31 T8 2 T19 1
valid_sources[0x50] 4411 1 T7 3 T8 1 T110 2
valid_sources[0x51] 4661 1 T2 2 T7 1 T11 6
valid_sources[0x52] 4746 1 T7 1 T43 2 T15 557
valid_sources[0x53] 4429 1 T110 1 T78 6 T15 537
valid_sources[0x54] 4868 1 T43 2 T39 2 T15 514
valid_sources[0x55] 4180 1 T2 2 T7 1 T11 1
valid_sources[0x56] 5637 1 T11 4 T39 1 T15 565
valid_sources[0x57] 4887 1 T43 1 T64 5 T78 1
valid_sources[0x58] 4203 1 T1 1 T78 1 T15 539
valid_sources[0x59] 5484 1 T7 1 T8 1 T15 531
valid_sources[0x5a] 4340 1 T19 1 T11 1 T15 505
valid_sources[0x5b] 4488 1 T43 2 T15 576 T16 301
valid_sources[0x5c] 5084 1 T19 1 T15 533 T60 2
valid_sources[0x5d] 4861 1 T8 1 T15 528 T16 90
valid_sources[0x5e] 4837 1 T78 2 T15 508 T37 1
valid_sources[0x5f] 5154 1 T15 580 T16 86 T135 1
valid_sources[0x60] 4318 1 T7 1 T31 2 T15 533
valid_sources[0x61] 4507 1 T2 1 T15 528 T16 159
valid_sources[0x62] 5361 1 T19 1 T110 2 T39 1
valid_sources[0x63] 4847 1 T15 531 T16 199 T41 2
valid_sources[0x64] 4454 1 T31 2 T15 565 T36 1
valid_sources[0x65] 4818 1 T15 518 T16 56 T17 704
valid_sources[0x66] 4651 1 T22 1 T15 552 T36 1
valid_sources[0x67] 5426 1 T2 1 T8 1 T19 1
valid_sources[0x68] 4688 1 T43 1 T25 1 T15 543
valid_sources[0x69] 4265 1 T7 1 T43 1 T110 1
valid_sources[0x6a] 5208 1 T2 1 T6 5 T11 1
valid_sources[0x6b] 4263 1 T12 1 T15 492 T37 3
valid_sources[0x6c] 4531 1 T7 1 T43 1 T11 2
valid_sources[0x6d] 4800 1 T21 2 T15 551 T16 63
valid_sources[0x6e] 4535 1 T11 2 T15 531 T16 93
valid_sources[0x6f] 4518 1 T7 3 T15 484 T16 65
valid_sources[0x70] 4505 1 T2 2 T43 1 T11 1
valid_sources[0x71] 4351 1 T7 1 T21 1 T78 1
valid_sources[0x72] 5603 1 T19 1 T43 1 T11 2
valid_sources[0x73] 4238 1 T6 3 T78 1 T15 554
valid_sources[0x74] 4210 1 T6 1 T7 1 T78 2
valid_sources[0x75] 3789 1 T43 1 T15 526 T16 161
valid_sources[0x76] 5167 1 T6 5 T7 1 T43 1
valid_sources[0x77] 4577 1 T78 3 T15 520 T16 73
valid_sources[0x78] 4191 1 T110 1 T78 1 T15 541
valid_sources[0x79] 5071 1 T43 1 T110 1 T78 1
valid_sources[0x7a] 4547 1 T43 2 T11 1 T110 1
valid_sources[0x7b] 4054 1 T15 551 T36 2 T37 1
valid_sources[0x7c] 4390 1 T19 1 T15 576 T37 1
valid_sources[0x7d] 5258 1 T25 1 T15 556 T16 121
valid_sources[0x7e] 4694 1 T7 3 T110 1 T15 526
valid_sources[0x7f] 5429 1 T15 523 T16 137 T82 1
valid_sources[0x80] 4990 1 T11 1 T15 517 T36 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 284226 1 T2 17 T3 12 T4 16
values[0x0] all_enables biggest_size 421057 1 T1 1 T9 2 T25 2
values[0x1] all_enables biggest_size 420645 1 T9 1 T25 2 T15 46111

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